From patchwork Wed May 25 15:04:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Westerberg X-Patchwork-Id: 9135681 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9006B607D9 for ; Wed, 25 May 2016 15:05:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 836E828164 for ; Wed, 25 May 2016 15:05:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 78186282DD; Wed, 25 May 2016 15:05:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 306CE282B3 for ; Wed, 25 May 2016 15:05:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753912AbcEYPFK (ORCPT ); Wed, 25 May 2016 11:05:10 -0400 Received: from mga09.intel.com ([134.134.136.24]:20164 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753537AbcEYPFJ (ORCPT ); Wed, 25 May 2016 11:05:09 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 25 May 2016 08:04:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,364,1459839600"; d="scan'208";a="974334365" Received: from black.fi.intel.com ([10.237.72.93]) by fmsmga001.fm.intel.com with ESMTP; 25 May 2016 08:04:58 -0700 Received: by black.fi.intel.com (Postfix, from userid 1001) id 35082E1; Wed, 25 May 2016 18:04:56 +0300 (EEST) From: Mika Westerberg To: Bjorn Helgaas Cc: Peter Wu , "Rafael J. Wysocki" , Lukas Wunner , linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, Valdis Kletnieks , Dave Airlie , Mika Westerberg Subject: [PATCH] PCI: Wait for 50ms after bridge is powered up Date: Wed, 25 May 2016 18:04:56 +0300 Message-Id: <1464188696-25782-1-git-send-email-mika.westerberg@linux.intel.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <20160524162833.GA30762@localhost> References: <20160524162833.GA30762@localhost> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PCI PM 1.2 specification requires minimum of 50ms before function on a bus is accessed after the bus is transitioned from B2 to B0. Now that we actually power down bridges we should make sure the specification is followed accordingly. Signed-off-by: Mika Westerberg --- Hi Bjorn, Since this is only needed when bridges are powered down, I think it makes sense to put this to your pci/pm branch. drivers/pci/pci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e785dc260e72..e645a3d4f2e0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2361,7 +2361,12 @@ void pci_pm_init(struct pci_dev *dev) } dev->pm_cap = pm; - dev->d3_delay = PCI_PM_D3_WAIT; + /* + * PCI PM 1.2 specification requires minimum of 50ms before any + * function on the bus is accessed after the bus is transitioned + * from B2 to B0. + */ + dev->d3_delay = pci_is_bridge(dev) ? PCI_PM_BUS_WAIT : PCI_PM_D3_WAIT; dev->d3cold_delay = PCI_PM_D3COLD_WAIT; dev->bridge_d3 = pci_bridge_d3_possible(dev); dev->d3cold_allowed = true;