From patchwork Thu Jun 2 04:33:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Derek Basehore X-Patchwork-Id: 9149003 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DB1C26074E for ; Thu, 2 Jun 2016 04:34:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D1AEC26B39 for ; Thu, 2 Jun 2016 04:34:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C61EB2823D; Thu, 2 Jun 2016 04:34:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47E6C26B39 for ; Thu, 2 Jun 2016 04:34:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751922AbcFBEeT (ORCPT ); Thu, 2 Jun 2016 00:34:19 -0400 Received: from mail-pf0-f170.google.com ([209.85.192.170]:33542 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751019AbcFBEdf (ORCPT ); Thu, 2 Jun 2016 00:33:35 -0400 Received: by mail-pf0-f170.google.com with SMTP id b124so26319367pfb.0 for ; Wed, 01 Jun 2016 21:33:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hSINYrVEMBMEwJ2eRDbKBgunzARwDTEUusWatw9Z7LA=; b=OmwhK0oXa/CNUyByNbGKCFPjGhE610bWpqcjUeqieCKmTME3EWpa0OsqqbCGXtRL4L aUGCuQ69Uy2ObZ2oo5mQDk426uZr3ANic++l/0F4n+5m+aXoaud1v1xmQQ7c0xi0DJC0 QX8kXg3dsKZalleDSxrF0TTSw/dXjt4AGAcwI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hSINYrVEMBMEwJ2eRDbKBgunzARwDTEUusWatw9Z7LA=; b=aIjs2Ip6zN/mJ/lsdfWbS89bbvSA94sl+N8+hdqT/FRkYPJYWrSQs+qJG3i2voP5Ii esVwBMMolN2snEE9RsjlEoz97dLGKCL+gPOk3VOn5WDL04GDgYKpS9Iz71c1Cclszd8t wbPm4vtYC93so62IdeKgETVHvdCo0WaQiH5en/wC1I5Jl9SFIJn4s6OggZzEsT+HjesS 7gUfNHam+5T3dXR2TMUyRwGpwyIg7UcFxbABnlGKOr56g7b0NJGOlCnR/Ulh/wJyDfU/ r6Wb7mXYnFLD/LsCPVxnsFLGsg+FDGRr0pFeGMTLWh1FDXgANrs1Cc/Sw+pWta8rUDDP TXXg== X-Gm-Message-State: ALyK8tKK7cnN7D/d7jRY2UzaNalj/SsnH4Cht4T/n9zrz2fM1XgeeugV5/sH1xw/Si1v5kOT X-Received: by 10.98.65.209 with SMTP id g78mr695498pfd.163.1464842015190; Wed, 01 Jun 2016 21:33:35 -0700 (PDT) Received: from ketosis.mtv.corp.google.com ([172.22.65.104]) by smtp.gmail.com with ESMTPSA id w190sm3743142pfd.58.2016.06.01.21.33.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 01 Jun 2016 21:33:34 -0700 (PDT) From: dbasehore@chromium.org To: linux-kernel@vger.kernel.org Cc: dbasehore@chromium.org, linux-pm@vger.kernel.org, rjw@rjwysocki.net, pavel@ucw.cz, len.brown@intel.com, tglx@linutronix.de Subject: [PATCH 3/5] x86, apic: Add timed freeze support Date: Wed, 1 Jun 2016 21:33:27 -0700 Message-Id: <1464842009-21789-4-git-send-email-dbasehore@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1464842009-21789-1-git-send-email-dbasehore@chromium.org> References: <1464842009-21789-1-git-send-email-dbasehore@chromium.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Derek Basehore This adds support to the clock event devices created by apic to use timed freeze. The apic is able to run a timer during freeze with near izero impact on modern CPUs such as skylake. This will allow S0ix, suspend-to-idle, to be validated on Intel CPUs that support it. This is needed because bugs with power settings on the SoC can prevent S0ix entry. There is also no way to check this before idling all of the CPUs. Signed-off-by: Derek Basehore --- arch/x86/kernel/apic/apic.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 60078a6..f0c5f92 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -475,6 +475,26 @@ static int lapic_next_deadline(unsigned long delta, return 0; } +static bool lapic_event_expired(struct clock_event_device *evt) +{ + u32 cct; + + cct = apic_read(APIC_TMCCT); + return cct == 0; +} + +static bool lapic_deadline_expired(struct clock_event_device *evt) +{ + u64 msr; + + /* + * When the timer interrupt is triggered, the register is cleared, so a + * non-zero value indicates a pending timer event. + */ + rdmsrl(MSR_IA32_TSC_DEADLINE, msr); + return msr == 0; +} + static int lapic_timer_shutdown(struct clock_event_device *evt) { unsigned int v; @@ -529,12 +549,14 @@ static struct clock_event_device lapic_clockevent = { .name = "lapic", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP - | CLOCK_EVT_FEAT_DUMMY, + | CLOCK_EVT_FEAT_DUMMY | + CLOCK_EVT_FEAT_FREEZE, .shift = 32, .set_state_shutdown = lapic_timer_shutdown, .set_state_periodic = lapic_timer_set_periodic, .set_state_oneshot = lapic_timer_set_oneshot, .set_next_event = lapic_next_event, + .event_expired = lapic_event_expired, .broadcast = lapic_timer_broadcast, .rating = 100, .irq = -1, @@ -562,6 +584,7 @@ static void setup_APIC_timer(void) levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_DUMMY); levt->set_next_event = lapic_next_deadline; + levt->event_expired = lapic_deadline_expired; clockevents_config_and_register(levt, (tsc_khz / TSC_DIVISOR) * 1000, 0xF, ~0UL);