From patchwork Wed Oct 26 16:37:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 9397677 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0203E60477 for ; Wed, 26 Oct 2016 16:41:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F53629C55 for ; Wed, 26 Oct 2016 16:41:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1407829C64; Wed, 26 Oct 2016 16:41:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89F8F29C5F for ; Wed, 26 Oct 2016 16:41:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933774AbcJZQkp (ORCPT ); Wed, 26 Oct 2016 12:40:45 -0400 Received: from conuserg-08.nifty.com ([210.131.2.75]:29821 "EHLO conuserg-08.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753399AbcJZQkn (ORCPT ); Wed, 26 Oct 2016 12:40:43 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-08.nifty.com with ESMTP id u9QGctqX026374; Thu, 27 Oct 2016 01:39:02 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com u9QGctqX026374 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1477499943; bh=qZ4ATz6XCHRpzq6r/MnSRaBv6MAF+1izcqPUUs/7Ngc=; h=From:To:Cc:Subject:Date:From; b=M/EJALcbFfFujBoOBl7uyW5Cj1QsuKfBzQlyhxt1Mpn9Jv2YPtDYNHq8a/pIXHkTQ 1UdBIY7bOq7OVf7UMzyW2koyQLKKYpnoqUdVXp1O4IJBVz2LgYNmXQ0qOC918Caw01 dzjf/u7mbNRfTPO5pc0+kRke02Y6M7i5yHkxt263ymDSIkpOeuHrxyfNwLbQSv2rqc eNubiTGIqfUaEOQl12GI/0xo3/1clYdI0PXehAkvLLry/bEQGj+K723IKOTjIYysm7 +wMKFnxAAlXyiXHicP87x37RCGlNb+hYRR1lL+lFK/NVJTlptJnXBZ4bsWOILoU2XE F54eGdNYZiEDA== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Viresh Kumar , linux-pm@vger.kernel.org, Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King Subject: [PATCH 1/2] ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoC Date: Thu, 27 Oct 2016 01:37:38 +0900 Message-Id: <1477499859-12415-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Signed-off-by: Masahiro Yamada Acked-by: Viresh Kumar --- arch/arm/boot/dts/uniphier-pro5.dtsi | 74 ++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 5357ea9..5bd6068 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -56,16 +56,90 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + }; + }; + + cpu_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp@116667000 { + opp-hz = /bits/ 64 <116667000>; + clock-latency-ns = <300>; + }; + opp@150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp@175000000 { + opp-hz = /bits/ 64 <175000000>; + clock-latency-ns = <300>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp@233334000 { + opp-hz = /bits/ 64 <233334000>; + clock-latency-ns = <300>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp@350000000 { + opp-hz = /bits/ 64 <350000000>; + clock-latency-ns = <300>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp@466667000 { + opp-hz = /bits/ 64 <466667000>; + clock-latency-ns = <300>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp@700000000 { + opp-hz = /bits/ 64 <700000000>; + clock-latency-ns = <300>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp@933334000 { + opp-hz = /bits/ 64 <933334000>; + clock-latency-ns = <300>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; + }; + opp@1400000000 { + opp-hz = /bits/ 64 <1400000000>; + clock-latency-ns = <300>; }; };