From patchwork Wed Oct 26 16:37:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 9397675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BCD2060231 for ; Wed, 26 Oct 2016 16:41:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAFD429C55 for ; Wed, 26 Oct 2016 16:41:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CE3F329C68; Wed, 26 Oct 2016 16:41:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 48CBE29C55 for ; Wed, 26 Oct 2016 16:41:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932188AbcJZQko (ORCPT ); Wed, 26 Oct 2016 12:40:44 -0400 Received: from conuserg-08.nifty.com ([210.131.2.75]:29820 "EHLO conuserg-08.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753255AbcJZQkn (ORCPT ); Wed, 26 Oct 2016 12:40:43 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-08.nifty.com with ESMTP id u9QGctqY026374; Thu, 27 Oct 2016 01:39:10 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com u9QGctqY026374 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1477499950; bh=SClyH+9Z+sjd5M9u1hym9QkZtvQjI2esrzlecxLLnlE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uP5yG1YcPDbMhN4K/5tU6UHH+duAg8+2q/9PufhLiZeoIU/t2YfgjOnL+rm/COa/v EcyLeudgN3NXX/pkjjTZmI+F7wk5UIUexVeJyPct1rAYjcfc6VAKqTfkSuxG6vky0Z KPakwNrpawhtxPFej3qBKN8UtNGZxBn+fbYr7JCd0MB0wwYmIY0Cqp7YsJIx02838C 9MTUd7NHLknCr85ZNu9/DRknBO8yKfB3g/o8XcmfcYPG31P0mPk3wrlbYSS7jIug5k tYeYQol8gQRgzSRWEJL870FpWtG6h4eNwal+AVb/gYRT4Z3kVS22P6zAD2O8XvxOjS SLANWVxoh2KbQ== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Viresh Kumar , linux-pm@vger.kernel.org, Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King Subject: [PATCH 2/2] ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoC Date: Thu, 27 Oct 2016 01:37:39 +0900 Message-Id: <1477499859-12415-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477499859-12415-1-git-send-email-yamada.masahiro@socionext.com> References: <1477499859-12415-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-pxs2.dtsi | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 950f07b..83ba3e6 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -56,32 +56,78 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; + operating-points-v2 = <&cpu_opp>; + }; + }; + + cpu_opp: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + clock-latency-ns = <300>; + }; + opp@150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <300>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <300>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + clock-latency-ns = <300>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + clock-latency-ns = <300>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <300>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <300>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <300>; }; };