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[82.242.157.225]) by smtp.gmail.com with ESMTPSA id x140sm3769666wme.19.2016.12.02.07.39.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Dec 2016 07:39:30 -0800 (PST) From: Bartosz Golaszewski To: Kevin Hilman , Michael Turquette , Sekhar Nori , Peter Ujfalusi , Russell King , Viresh Kumar , Boris Brezillon , "Rafael J. Wysocki" , Richard Weinberger , David Woodhouse , Brian Norris , Marek Vasut , Cyrille Pitchen Cc: LKML , arm-soc , linux-pm@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v2 3/3] ARM: da850: fix da850_set_pll0rate() Date: Fri, 2 Dec 2016 16:38:54 +0100 Message-Id: <1480693134-31324-4-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1480693134-31324-1-git-send-email-bgolaszewski@baylibre.com> References: <1480693134-31324-1-git-send-email-bgolaszewski@baylibre.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This function is broken - its second argument is an index to the freq table, not the requested clock rate in Hz. It leads to an oops when called from clk_set_rate() since this argument isn't bounds checked either. Fix it by iterating over the array of supported frequencies and selecting a one that matches or returning -EINVAL for unsupported rates. Also: update the davinci cpufreq driver. It's the only user of this clock and currently it passes the cpufreq table index to clk_set_rate(), which is confusing. Make it pass the requested clock rate in Hz. Signed-off-by: Bartosz Golaszewski Acked-by: Viresh Kumar --- arch/arm/mach-davinci/da850.c | 22 ++++++++++++++++++---- drivers/cpufreq/davinci-cpufreq.c | 2 +- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index a55101c..92e3303 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1179,14 +1179,28 @@ static int da850_set_armrate(struct clk *clk, unsigned long index) return clk_set_rate(pllclk, index); } -static int da850_set_pll0rate(struct clk *clk, unsigned long index) +static int da850_set_pll0rate(struct clk *clk, unsigned long rate) { - unsigned int prediv, mult, postdiv; - struct da850_opp *opp; struct pll_data *pll = clk->pll_data; + struct cpufreq_frequency_table *freq; + unsigned int prediv, mult, postdiv; + struct da850_opp *opp = NULL; int ret; - opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; + for (freq = da850_freq_table; + freq->frequency != CPUFREQ_TABLE_END; freq++) { + /* requested_rate is in Hz, freq->frequency is in KHz */ + unsigned long freq_rate = freq->frequency * 1000; + + if (freq_rate == rate) { + opp = (struct da850_opp *)freq->driver_data; + break; + } + } + + if (opp == NULL) + return -EINVAL; + prediv = opp->prediv; mult = opp->mult; postdiv = opp->postdiv; diff --git a/drivers/cpufreq/davinci-cpufreq.c b/drivers/cpufreq/davinci-cpufreq.c index b95a872..d54a27c 100644 --- a/drivers/cpufreq/davinci-cpufreq.c +++ b/drivers/cpufreq/davinci-cpufreq.c @@ -55,7 +55,7 @@ static int davinci_target(struct cpufreq_policy *policy, unsigned int idx) return ret; } - ret = clk_set_rate(armclk, idx); + ret = clk_set_rate(armclk, new_freq * 1000); if (ret) return ret;