From patchwork Fri May 5 15:26:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 9713805 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7BB6060387 for ; Fri, 5 May 2017 15:28:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6676D28685 for ; Fri, 5 May 2017 15:28:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B43228652; Fri, 5 May 2017 15:28:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 137AF28685 for ; Fri, 5 May 2017 15:28:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754705AbdEEP16 (ORCPT ); Fri, 5 May 2017 11:27:58 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:46063 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753362AbdEEP03 (ORCPT ); Fri, 5 May 2017 11:26:29 -0400 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 559064412; Fri, 05 May 2017 23:26:26 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Fri, 5 May 2017 23:26:24 +0800 From: To: , , , , , , , , , , , , , , , CC: , Sean Wang , Pi-Cheng Chen Subject: [PATCH 2/6] clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs Date: Fri, 5 May 2017 23:26:10 +0800 Message-ID: <1493997974-17699-3-git-send-email-sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1493997974-17699-1-git-send-email-sean.wang@mediatek.com> References: <1493997974-17699-1-git-send-email-sean.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sean Wang The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen Signed-off-by: Sean Wang --- drivers/clk/mediatek/clk-mt2701.c | 8 ++++++++ include/dt-bindings/clock/mt2701-clk.h | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 6f26e6a..9598889 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -20,6 +20,7 @@ #include "clk-mtk.h" #include "clk-gate.h" +#include "clk-cpumux.h" #include @@ -493,6 +494,10 @@ static const char * const cpu_parents[] = { "mmpll" }; +static const struct mtk_composite cpu_muxes[] __initconst = { + MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2), +}; + static const struct mtk_composite top_muxes[] = { MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3, 7, CLK_IS_CRITICAL), @@ -759,6 +764,9 @@ static void mtk_infrasys_init_early(struct device_node *node) mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), infra_clk_data); + mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), + infra_clk_data); + r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h index 2062c67..551f760 100644 --- a/include/dt-bindings/clock/mt2701-clk.h +++ b/include/dt-bindings/clock/mt2701-clk.h @@ -221,7 +221,8 @@ #define CLK_INFRA_PMICWRAP 17 #define CLK_INFRA_DDCCI 18 #define CLK_INFRA_CLK_13M 19 -#define CLK_INFRA_NR 20 +#define CLK_INFRA_CPUSEL 20 +#define CLK_INFRA_NR 21 /* PERICFG */