From patchwork Tue Jun 12 11:02:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 10460047 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 18FF260348 for ; Tue, 12 Jun 2018 11:03:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F3E28285AA for ; Tue, 12 Jun 2018 11:03:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E8090286D0; Tue, 12 Jun 2018 11:03:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 73E8C285AA for ; Tue, 12 Jun 2018 11:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933315AbeFLLCx (ORCPT ); Tue, 12 Jun 2018 07:02:53 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:42516 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933295AbeFLLCv (ORCPT ); Tue, 12 Jun 2018 07:02:51 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 82299606DB; Tue, 12 Jun 2018 11:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1528801370; bh=nS/EvWej8YdR5bI3gWtIx6sPrqHWhvpXYE7WZFg9lYw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QWXlfiv5ZO2Hfp18lRpreAxUe3gypbBMmc4+wjd+PnhrZif0k0eHLy+SwLEjhnvkc XuiX4v+CemD6nDft9QWTCw2CK1sZiMa0o/NZyhxJJppIrluteMXlPWGcMEFTE8ZRrL ic7rWGjJkrJiteCsnGEg54lWjH3VKVUCrX8IQOsg= Received: from tdas-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tdas@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B3F6E606DB; Tue, 12 Jun 2018 11:02:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1528801369; bh=nS/EvWej8YdR5bI3gWtIx6sPrqHWhvpXYE7WZFg9lYw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=omwck2USmFfLxmDOvwb1h9770vjjQJJoSXfGxCsN3a/cELJM7li8o3dOsT2DHFo5v GnKsW3F0ELg0DsAIPwdHTld2tCts4C71WurjTRPMtTHFKO8BKX2XmZx5H43Qzu4oWi tqi1VKerGTaeI2gdqwJiOV6ik6DRXRCZC9fYW4Mg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B3F6E606DB Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=tdas@codeaurora.org From: Taniya Das To: "Rafael J. Wysocki" , Viresh Kumar , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Stephen Boyd Cc: Rajendra Nayak , devicetree@vger.kernel.org, robh@kernel.org, skannan@codeaurora.org, Taniya Das Subject: [PATCH v4 1/2] dt-bindings: cpufreq: Introduce QCOM CPUFREQ FW bindings Date: Tue, 12 Jun 2018 16:32:34 +0530 Message-Id: <1528801355-18719-2-git-send-email-tdas@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1528801355-18719-1-git-send-email-tdas@codeaurora.org> References: <1528801355-18719-1-git-send-email-tdas@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's SoCs. This is required for managing the cpu frequency transitions which are controlled by firmware. Signed-off-by: Taniya Das --- .../bindings/cpufreq/cpufreq-qcom-fw.txt | 173 +++++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt new file mode 100644 index 0000000..e3087ec --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-fw.txt @@ -0,0 +1,173 @@ +Qualcomm Technologies, Inc. CPUFREQ Bindings + +CPUFREQ FW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) +SoCs to manage frequency in hardware. It is capable of controlling frequency +for multiple clusters. + +Properties: +- compatible + Usage: required + Value type: + Definition: must be "qcom,cpufreq-fw". + +* Property qcom,freq-domain +Devices supporting freq-domain must set their "qcom,freq-domain" property with +phandle to a freq_domain_table in their DT node. + +* Frequency Domain Table Node + +This describes the frequency domain belonging to a device. +This node can have following properties: + +- reg + Usage: required + Value type: + Definition: Addresses and sizes for the memory of the perf + , lut and enable bases. + perf - indicates the base address for the desired + performance state to be set. + lut - indicates the look up table base address for the + cpufreq driver to read frequencies. + enable - indicates the enable register for firmware. +- reg-names + Usage: required + Value type: + Definition: Address names. Must be "perf", "lut", "enable". + Must be specified in the same order as the reg property. + +Example: + +Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch +DCVS state together. + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&freq_domain_table0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&freq_domain_table0>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&freq_domain_table0>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&freq_domain_table0>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&freq_domain_table1>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&freq_domain_table1>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&freq_domain_table1>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&freq_domain_table1>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + qcom,cpufreq-fw { + compatible = "qcom,cpufreq-fw"; + + #address-cells = <1>; + #size-cells = <1>; + + freq_domain_table0 : freq_table0 { + reg = <0x17d43920 0x4>, <0x17d43110 0x500>, + <0x17d41000 0x4>; + reg-names = "perf", "lut", "enable"; + }; + + freq_domain_table1 : freq_table1 { + reg = <0x17d46120 0x4>, <0x17d45910 0x500>, + <0x17d45800 0x4> ; + reg-names = "perf", "lut", "enable"; + }; + };