From patchwork Thu Feb 21 10:18:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 10823503 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 026E215AC for ; Thu, 21 Feb 2019 10:19:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E548C29B75 for ; Thu, 21 Feb 2019 10:19:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D95A42A359; Thu, 21 Feb 2019 10:19:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 68E1929B75 for ; Thu, 21 Feb 2019 10:19:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727241AbfBUKTV (ORCPT ); Thu, 21 Feb 2019 05:19:21 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12373 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726151AbfBUKTU (ORCPT ); Thu, 21 Feb 2019 05:19:20 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 21 Feb 2019 02:19:27 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 21 Feb 2019 02:19:19 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 21 Feb 2019 02:19:19 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 10:19:18 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 10:19:18 +0000 Received: from niwei-ubuntu.nvidia.com (Not Verified[10.19.225.182]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 21 Feb 2019 02:19:18 -0800 From: Wei Ni To: , , CC: , , , , , , , Wei Ni Subject: [PATCH v2 10/12] arm64: dts: tegra210: set EDP interrupt line Date: Thu, 21 Feb 2019 18:18:45 +0800 Message-ID: <1550744327-4677-11-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1550744327-4677-1-git-send-email-wni@nvidia.com> References: <1550744327-4677-1-git-send-email-wni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550744367; bh=I7afLGSpQb3mqB8C0marJMfeWiqjYpL+/2LybdI+aUY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=P2cnKNby3qk0nwfeIJFInKRmfsoCZrV2VxpWb3bd+jMW1dcg3CJugg7tCxOUihgV1 xtvUpM3JjLxBY8H69Zgtu6JQkpHFKrEROwGrjNbC1TFMj+kD99cuiexW7LPpycgx1J BBZXMzMekuK2fFjD6tj0Zx/5tvhL5DraRTiiQqoQg2o956NpSmjBwue87kyERXzeco ig8E5hl0MVh2oOz90WS/N33z+WZygQ22JEqjZX0erox7FPwffef6xsxz7GLA/mDRCi a6LBgEkjszECczb/xb5lxl/VtFZONJ0P/WKVvJv6cA5J1CulxNHl1c/TqqBsBjVjAy xJopZ/EgJtKtg== Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set EDP interrupt line. Signed-off-by: Wei Ni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 551600513c1a..19966b9f5ce7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1402,7 +1402,8 @@ reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ reg-names = "soctherm-reg", "car-reg"; - interrupts = ; + interrupts = ; clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, <&tegra_car TEGRA210_CLK_SOC_THERM>; clock-names = "tsensor", "soctherm";