From patchwork Tue Nov 26 13:12:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11262223 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 173A9109A for ; Tue, 26 Nov 2019 13:13:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F30572073F for ; Tue, 26 Nov 2019 13:13:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727701AbfKZNNA (ORCPT ); Tue, 26 Nov 2019 08:13:00 -0500 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:58316 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727667AbfKZNM7 (ORCPT ); Tue, 26 Nov 2019 08:12:59 -0500 Received-SPF: Pass (esa1.microchip.iphmx.com: domain of Claudiu.Beznea@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa1.microchip.iphmx.com; envelope-from="Claudiu.Beznea@microchip.com"; x-sender="Claudiu.Beznea@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com -exists:%{i}.spf.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa1.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa1.microchip.iphmx.com; envelope-from="Claudiu.Beznea@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa1.microchip.iphmx.com; dkim=none (message not signed) header.i=none; spf=Pass smtp.mailfrom=Claudiu.Beznea@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: h5FouLdRP6eot3wz1FB/1SAuAhlFBgUkK2AcM7QjD1dxQIsFcBpCCyP12bLCIr+8/Vc91heksH fJwhk9kV6WeykU+0wJwjq+VHJaRPBc+f+Qm2UWScO861U4ebiG3u09k7JUSAaP8QMsCFK54t79 jeNH9rn5Ak/Ys7wbDdDIYdVmMKpEju6fSupHrDzXn6D5rd2jgydm/Kxd3nsDnke9YGLzI6Du47 cB2y0qyVwUu9PKKQAXDTRS4Mr5SzWZbTIp8bimL9ITElZx/QUZUdPb5Wm0WmPUe+33IHK/gBTR G0o= X-IronPort-AV: E=Sophos;i="5.69,245,1571727600"; d="scan'208";a="59777299" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Nov 2019 06:12:59 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 26 Nov 2019 06:12:54 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.85.251) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Tue, 26 Nov 2019 06:12:52 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH v2 01/17] ARM: at91: Kconfig: add sam9x60 pll config flag Date: Tue, 26 Nov 2019 15:12:05 +0200 Message-ID: <1574773941-20649-2-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574773941-20649-1-git-send-email-claudiu.beznea@microchip.com> References: <1574773941-20649-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add SAM9X60's pll config flag. It was first used in commit a436c2a447e5 ("clk: at91: add sam9x60 PLL driver"). Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index af41725fcc72..262b550d7329 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -154,6 +154,9 @@ config HAVE_AT91_AUDIO_PLL config HAVE_AT91_I2S_MUX_CLK bool +config HAVE_AT91_SAM9X60_PLL + bool + config SOC_SAM_V4_V5 bool