From patchwork Fri Oct 23 08:24:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11852497 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB0F51580 for ; Fri, 23 Oct 2020 08:25:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B189B241A4 for ; Fri, 23 Oct 2020 08:25:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="r65d5i8g" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S460538AbgJWIZO (ORCPT ); Fri, 23 Oct 2020 04:25:14 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:39533 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S460534AbgJWIZM (ORCPT ); Fri, 23 Oct 2020 04:25:12 -0400 X-UUID: 5f0bcd56c56b4c558906e803db9aca9d-20201023 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=0VcRiI/47uBH8qw621lJkqfCixACdBgrTLwaebngM9Y=; b=r65d5i8gAyCDBYrLqsR7ei8d2pn+b/amXSMV2VYOCbA/0PKIWP5/Up19zNfAGrOvjrhNYCw4RMbhAprIKM9YRFqE6jXtzCTkQJVx0vrvWxRZLA/XbcJAa+vrRT+5pX9wAzht3ceN/M8HHHt+LojLjgtCrov4IUXJ8JtijlVsZ70=; X-UUID: 5f0bcd56c56b4c558906e803db9aca9d-20201023 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1743175875; Fri, 23 Oct 2020 16:25:01 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Oct 2020 16:24:59 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Oct 2020 16:24:59 +0800 From: Hector Yuan To: , , , Rob Herring , "Rafael J. Wysocki" , Viresh Kumar , Maxime Ripard , Santosh Shilimkar , Amit Kucheria , Stephen Boyd , Ulf Hansson , Dave Gerlach , Florian Fainelli , Robin Murphy , Lorenzo Pieralisi , CC: , , Subject: [PATCH v1 3/6] dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW Date: Fri, 23 Oct 2020 16:24:50 +0800 Message-ID: <1603441493-18554-4-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> References: <1603441493-18554-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Hector.Yuan" Add devicetree bindings for MediaTek HW driver. Signed-off-by: Hector.Yuan --- .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml new file mode 100644 index 0000000..a99f44f --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek's CPUFREQ Bindings + +maintainers: + - Hector Yuan + +description: + CPUFREQ HW is a hardware engine used by MediaTek + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + const: mediatek,cpufreq-hw + + reg: + minItems: 1 + maxItems: 2 + description: | + Addresses and sizes for the memory of the HW bases in each frequency domain. + +required: + - compatible + - reg + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + cpufreq_hw: cpufreq@11bc00 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x11bc10 0 0x8c>, + <0 0x11bca0 0 0x8c>; + }; + }; + + + +