From patchwork Fri Aug 7 21:00:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Torokhov X-Patchwork-Id: 6973121 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2C4C59F373 for ; Fri, 7 Aug 2015 21:01:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8459A20620 for ; Fri, 7 Aug 2015 21:00:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A683A2061B for ; Fri, 7 Aug 2015 21:00:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754011AbbHGVA4 (ORCPT ); Fri, 7 Aug 2015 17:00:56 -0400 Received: from mail-pa0-f52.google.com ([209.85.220.52]:34569 "EHLO mail-pa0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753837AbbHGVA4 (ORCPT ); Fri, 7 Aug 2015 17:00:56 -0400 Received: by pawu10 with SMTP id u10so96233601paw.1 for ; Fri, 07 Aug 2015 14:00:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-type:content-disposition:user-agent; bh=nMSu1+Xv6GAkjIInYWZ//n9xtV2SUYktQH4IE1WJ/Js=; b=ZAgRcNBJHEck9H7ke9x9sa4b2912Ae/PwEHU+MXSw5ZSBJcbLMPPfFvEwJ8yLIE+YF TmuaoCgvUSOpWYdasU6cly3DDZHEamqrEqtzJojH82cshXurPZgNjDwFm9BBG/tEs967 IRbkRpWYKt0Num5SsbN7yRJUrML3R/9KcQl6wO4LtUFvhfJOjTBqCJ/71Km/cDh94w2u 0gNxgifzXXV1R32ScEIDvqrCP/4zQ5dIYNB/L9a9kARwAJIpBsWuDqNTASMOEtm3zOhI PGYig3ZipN8yqGHdf9njEyHCiydEm3pZ9QuSNTaKpIO8LW4lYLIKh/I5NgKvrNdJA83D D/GA== X-Gm-Message-State: ALoCoQlAj3/IjweYxdeM12ImL6J80enSz7GPKsFbWTqyHZhSXB0FILKvToxOUNSs43bjnSGSEbJE X-Received: by 10.66.90.166 with SMTP id bx6mr18662807pab.76.1438981254339; Fri, 07 Aug 2015 14:00:54 -0700 (PDT) Received: from dtor-ws ([2620:0:1000:1301:fda8:35d:f03a:6572]) by smtp.gmail.com with ESMTPSA id fv5sm11159471pdb.19.2015.08.07.14.00.53 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 07 Aug 2015 14:00:54 -0700 (PDT) Date: Fri, 7 Aug 2015 14:00:52 -0700 From: Dmitry Torokhov To: Heiko Stuebner Cc: Eduardo Valentin , Caesar Wang , dianders@chromium.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] thermal: rockhip: fix setting thermal shutdown polarity Message-ID: <20150807210052.GA34032@dtor-ws> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When requested thermal shutdown signal polarity is low we need to make sure that the bit representing high level of signal is reset, and not set all other bits in that register. Also rename TSADCV2_INT_PD_CLEAR to TSADCV2_INT_PD_CLEAR_MASK to better reflect its nature. Signed-off-by: Dmitry Torokhov --- drivers/thermal/rockchip_thermal.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 93ee307..4d5b7d4 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -106,16 +106,14 @@ struct rockchip_thermal_data { #define TSADCV2_AUTO_PERIOD_HT 0x6c #define TSADCV2_AUTO_EN BIT(0) -#define TSADCV2_AUTO_DISABLE ~BIT(0) #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) -#define TSADCV2_AUTO_TSHUT_POLARITY_LOW ~BIT(8) #define TSADCV2_INT_SRC_EN(chn) BIT(chn) #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) -#define TSADCV2_INT_PD_CLEAR ~BIT(8) +#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) #define TSADCV2_DATA_MASK 0xfff #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 @@ -244,10 +242,10 @@ static void rk_tsadcv2_initialize(void __iomem *regs, enum tshut_polarity tshut_polarity) { if (tshut_polarity == TSHUT_HIGH_ACTIVE) - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_HIGH), + writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON); else - writel_relaxed(0 | (TSADCV2_AUTO_TSHUT_POLARITY_LOW), + writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, regs + TSADCV2_AUTO_CON); writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); @@ -264,7 +262,7 @@ static void rk_tsadcv2_irq_ack(void __iomem *regs) u32 val; val = readl_relaxed(regs + TSADCV2_INT_PD); - writel_relaxed(val & TSADCV2_INT_PD_CLEAR, regs + TSADCV2_INT_PD); + writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); } static void rk_tsadcv2_control(void __iomem *regs, bool enable)