From patchwork Tue Mar 28 17:30:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9650297 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D6C7F601E9 for ; Tue, 28 Mar 2017 17:38:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C219120243 for ; Tue, 28 Mar 2017 17:38:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B4A4D2845F; Tue, 28 Mar 2017 17:38:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 45D7220243 for ; Tue, 28 Mar 2017 17:38:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752808AbdC1RiT (ORCPT ); Tue, 28 Mar 2017 13:38:19 -0400 Received: from hermes.aosc.io ([172.82.152.187]:34688 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755342AbdC1RiS (ORCPT ); Tue, 28 Mar 2017 13:38:18 -0400 X-Greylist: delayed 453 seconds by postgrey-1.27 at vger.kernel.org; Tue, 28 Mar 2017 13:38:18 EDT Received: from localhost.localdomain (unknown [120.236.174.154]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id B593E802DF; Tue, 28 Mar 2017 17:30:43 +0000 (UTC) From: Icenowy Zheng To: Lee Jones , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jonathan Cameron , Zhang Rui , Quentin Schulz Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, Icenowy Zheng Subject: [RFC PATCH 1/3] dt-bindings: update the Allwinner GPADC device tree binding for H3 Date: Wed, 29 Mar 2017 01:30:11 +0800 Message-Id: <20170328173013.16539-2-icenowy@aosc.io> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170328173013.16539-1-icenowy@aosc.io> References: <20170328173013.16539-1-icenowy@aosc.io> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Allwinner H3 features a thermal sensor like the one in A33, but has its register re-arranged, the clock divider moved to CCU (originally the clock divider is in ADC) and added a pair of bus clock and reset. Update the binding document to cover H3. Signed-off-by: Icenowy Zheng --- .../devicetree/bindings/mfd/sun4i-gpadc.txt | 23 ++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt index badff3611a98..7753133ca0ff 100644 --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt @@ -4,12 +4,20 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor and sometimes as a touchscreen controller. Required properties: - - compatible: "allwinner,sun8i-a33-ths", + - compatible: must contain one of the following compatibles: + - "allwinner,sun8i-a33-ths" + - "allwinner,sun8i-h3-ths" - reg: mmio address range of the chip, - #thermal-sensor-cells: shall be 0, - #io-channel-cells: shall be 0, -Example: +Required properties for the following compatibles: + - "allwinner,sun8i-h3-ths" + - clocks: the bus clock and the input clock of the ADC, + - clock-names: should be "bus" and "ths", + - resets: the bus reset of the ADC, + +Example for A33: ths: ths@01c25000 { compatible = "allwinner,sun8i-a33-ths"; reg = <0x01c25000 0x100>; @@ -17,6 +25,17 @@ Example: #io-channel-cells = <0>; }; +Example for H3: + ths: ths@01c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x100>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "ths"; + resets = <&ccu RST_BUS_THS>; + #thermal-sensor-cells = <0>; + #io-channel-cells = <0>; + }; + sun4i, sun5i and sun6i SoCs are also supported via the older binding: sun4i resistive touchscreen controller