| Message ID | 20170723102749.17323-7-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > The CPUX clock, which is the main clock of the ARM core on Allwinner H3, > can be adjusted by changing the frequency of the PLL_CPUX clock. > > Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX > clock can be adjusted when adjusting the CPUX clock. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Reviewed-by: Chen-Yu Tsai <wens@csie.org>
On 07/23, Icenowy Zheng wrote: > The CPUX clock, which is the main clock of the ARM core on Allwinner H3, > can be adjusted by changing the frequency of the PLL_CPUX clock. > > Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX > clock can be adjusted when adjusting the CPUX clock. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- Acked-by: Stephen Boyd <sboyd@codeaurora.org>
On Mon, Jul 24, 2017 at 11:10 AM, Chen-Yu Tsai <wens@csie.org> wrote: > On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote: >> The CPUX clock, which is the main clock of the ARM core on Allwinner H3, >> can be adjusted by changing the frequency of the PLL_CPUX clock. >> >> Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX >> clock can be adjusted when adjusting the CPUX clock. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") > Reviewed-by: Chen-Yu Tsai <wens@csie.org> Applied for 4.14 with the Fixes tag and Stephen's ack. ChenYu
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 406d0aac9fd6..4cdbc88f2783 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpux" , "pll-cpux" }; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, - 0x050, 16, 2, CLK_IS_CRITICAL); + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
The CPUX clock, which is the main clock of the ARM core on Allwinner H3, can be adjusted by changing the frequency of the PLL_CPUX clock. Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX clock can be adjusted when adjusting the CPUX clock. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)