From patchwork Tue Aug 22 13:17:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 9915161 X-Patchwork-Delegate: rjw@sisk.pl Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 012D0603F9 for ; Tue, 22 Aug 2017 13:17:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC38F28699 for ; Tue, 22 Aug 2017 13:17:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E106F28764; Tue, 22 Aug 2017 13:17:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A78028699 for ; Tue, 22 Aug 2017 13:17:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932859AbdHVNRu (ORCPT ); Tue, 22 Aug 2017 09:17:50 -0400 Received: from mail-lf0-f46.google.com ([209.85.215.46]:35523 "EHLO mail-lf0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932657AbdHVNRu (ORCPT ); Tue, 22 Aug 2017 09:17:50 -0400 Received: by mail-lf0-f46.google.com with SMTP id k186so23467006lfe.2 for ; Tue, 22 Aug 2017 06:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=I7GfY+hDh9HmlPcGekOlb4QvepOZZPgSSh3sVvy3v5M=; b=eLDZuYTyO7a0ofGLZVtNG3uTXQohOWGRfoL48kaJ5RVhq2wuSAfGhkBvttHCKWhpc1 APCpKRQoZLjzz0FOsWefx7TGBbNUhURxV4+SNIA1YTRxA3+cmpL1uN/2ukoF8W7DKKw7 IBmWste/AHf+DSVLTv5UwUR/NKOcl9vEUoyGM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=I7GfY+hDh9HmlPcGekOlb4QvepOZZPgSSh3sVvy3v5M=; b=bZ7G9pQBk1Xib/zZLh1mLazpEXBA6Idn4P9DdAEllZ8oBSkoc8LopYyjOusKwuWgC7 lyWMYjJ1ZVGynCxR0tvf1uvN/Bg7wruBZoZTmdj7Q9i0Ji4T5ZrQWwrJ0XTi84yeW3/r 0Ue3qz2lrMjJPlD8usBK+sJFkdkkOjDvVmVy+zWhnpLiGj+Q6Aeam0v74yHXSmKLVT/E zN3xsQEVqeoAhVjjwmBPLp0QCxRObelKPbfu2C8KUPPV1T5fX8w33N7LTNnNrHBfTxVB CnCo8RFP+1tN8RsE7rxqnMG6W98GmUFf1dmO3XWKeQv+zmYUesIkMKTnR9CFLrRY1OO4 CAiQ== X-Gm-Message-State: AHYfb5hW4D5NZDlw7WumuSWyIapoTiDli3wX6qqaG6xIJO1hCNuI4kHI uoUOvxW7uTLblzyA X-Received: by 10.46.64.73 with SMTP id n70mr330554lja.120.1503407868481; Tue, 22 Aug 2017 06:17:48 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id 193sm2715984ljj.30.2017.08.22.06.17.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 06:17:47 -0700 (PDT) From: Linus Walleij To: "Rafael J . Wysocki" , Viresh Kumar , Lee Jones Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Ulf Hansson , Linus Walleij Subject: [PATCH 2/3 v3] mfd: db8500-prcmu: Get rid of cpufreq dependency Date: Tue, 22 Aug 2017 15:17:40 +0200 Message-Id: <20170822131741.23473-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170822131741.23473-1-linus.walleij@linaro.org> References: <20170822131741.23473-1-linus.walleij@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The ARMSS clock, also known as the operating point of the CPU, should not cross-depend on cpufreq like this. Move the code to use just frequencies and remove the false frequency (1GHz) and put in the actual frequency provided by the ARMSS clock (998400000 Hz) as part of the process. After this and the related cpufreq patch, the DB8500 will simply use the standard DT cpufreq driver to change the operating points through the common clock framework using the ARMSS clock. Acked-by: Lee Jones Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Fixed freq table indentation so both checkpatch and Lee are happy. --- drivers/mfd/db8500-prcmu.c | 62 ++++++++++++++++------------------------------ 1 file changed, 21 insertions(+), 41 deletions(-) diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 5c739ac752e8..5970b8def548 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include #include "dbx500-prcmu-regs.h" @@ -1692,32 +1691,27 @@ static long round_clock_rate(u8 clock, unsigned long rate) return rounded_rate; } -/* CPU FREQ table, may be changed due to if MAX_OPP is supported. */ -static struct cpufreq_frequency_table db8500_cpufreq_table[] = { - { .frequency = 200000, .driver_data = ARM_EXTCLK,}, - { .frequency = 400000, .driver_data = ARM_50_OPP,}, - { .frequency = 800000, .driver_data = ARM_100_OPP,}, - { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */ - { .frequency = CPUFREQ_TABLE_END,}, +static const unsigned long armss_freqs[] = { + 200000000, + 400000000, + 800000000, + 998400000 }; static long round_armss_rate(unsigned long rate) { - struct cpufreq_frequency_table *pos; - long freq = 0; - - /* cpufreq table frequencies is in KHz. */ - rate = rate / 1000; + unsigned long freq = 0; + int i; /* Find the corresponding arm opp from the cpufreq table. */ - cpufreq_for_each_entry(pos, db8500_cpufreq_table) { - freq = pos->frequency; - if (freq == rate) + for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) { + freq = armss_freqs[i]; + if (rate <= freq) break; } /* Return the last valid value, even if a match was not found. */ - return freq * 1000; + return freq; } #define MIN_PLL_VCO_RATE 600000000ULL @@ -1854,21 +1848,23 @@ static void set_clock_rate(u8 clock, unsigned long rate) static int set_armss_rate(unsigned long rate) { - struct cpufreq_frequency_table *pos; - - /* cpufreq table frequencies is in KHz. */ - rate = rate / 1000; + unsigned long freq; + u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP }; + int i; /* Find the corresponding arm opp from the cpufreq table. */ - cpufreq_for_each_entry(pos, db8500_cpufreq_table) - if (pos->frequency == rate) + for (i = 0; i < ARRAY_SIZE(armss_freqs); i++) { + freq = armss_freqs[i]; + if (rate == freq) break; + } - if (pos->frequency != rate) + if (rate != freq) return -EINVAL; /* Set the new arm opp. */ - return db8500_prcmu_set_arm_opp(pos->driver_data); + pr_debug("SET ARM OPP 0x%02x\n", opps[i]); + return db8500_prcmu_set_arm_opp(opps[i]); } static int set_plldsi_rate(unsigned long rate) @@ -3049,12 +3045,6 @@ static const struct mfd_cell db8500_prcmu_devs[] = { .pdata_size = sizeof(db8500_regulators), }, { - .name = "cpufreq-ux500", - .of_compatible = "stericsson,cpufreq-ux500", - .platform_data = &db8500_cpufreq_table, - .pdata_size = sizeof(db8500_cpufreq_table), - }, - { .name = "cpuidle-dbx500", .of_compatible = "stericsson,cpuidle-dbx500", }, @@ -3067,14 +3057,6 @@ static const struct mfd_cell db8500_prcmu_devs[] = { }, }; -static void db8500_prcmu_update_cpufreq(void) -{ - if (prcmu_has_arm_maxopp()) { - db8500_cpufreq_table[3].frequency = 1000000; - db8500_cpufreq_table[3].driver_data = ARM_MAX_OPP; - } -} - static int db8500_prcmu_register_ab8500(struct device *parent) { struct device_node *np; @@ -3160,8 +3142,6 @@ static int db8500_prcmu_probe(struct platform_device *pdev) prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); - db8500_prcmu_update_cpufreq(); - err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs, ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain); if (err) {