From patchwork Tue Nov 28 15:26:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 10080659 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B180360234 for ; Tue, 28 Nov 2017 15:29:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A7EBC293FD for ; Tue, 28 Nov 2017 15:29:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A5FF1293F0; Tue, 28 Nov 2017 15:29:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5CFE6293FE for ; Tue, 28 Nov 2017 15:29:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753910AbdK1P2A (ORCPT ); Tue, 28 Nov 2017 10:28:00 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:36942 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753719AbdK1P1y (ORCPT ); Tue, 28 Nov 2017 10:27:54 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 0B71120741; Tue, 28 Nov 2017 16:27:53 +0100 (CET) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.free-electrons.com (Postfix) with ESMTPSA id D228A20745; Tue, 28 Nov 2017 16:27:42 +0100 (CET) From: Alexandre Belloni To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Rob Herring , devicetree@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset binding Date: Tue, 28 Nov 2017 16:26:36 +0100 Message-Id: <20171128152643.20463-7-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171128152643.20463-1-alexandre.belloni@free-electrons.com> References: <20171128152643.20463-1-alexandre.belloni@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add binding documentation for the Microsemi Ocelot reset block. Signed-off-by: Alexandre Belloni --- Cc: Rob Herring Cc: devicetree@vger.kernel.org To: Sebastian Reichel Cc: linux-pm@vger.kernel.org .../bindings/power/reset/ocelot-reset.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt new file mode 100644 index 000000000000..2d3f2c21fadd --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -0,0 +1,24 @@ +Microsemi Ocelot reset driver + +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the +SoC MIPS core. + +Required Properties: + - compatible: "mscc,ocelot-chip-reset" + - mscc,cpucontrol: phandle to the CPU system control syscon block + +Example: + cpu_ctrl: syscon@70000000 { + compatible = "syscon"; + reg = <0x70000000 0x2c>; + }; + + syscon@71070000 { + compatible = "simple-mfd", "syscon"; + reg = <0x71070000 0x1c>; + + reset { + compatible = "mscc,ocelot-chip-reset"; + mscc,cpucontrol = <&cpu_ctrl>; + }; + };