From patchwork Mon Dec 18 14:36:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10119661 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3EA6160390 for ; Mon, 18 Dec 2017 14:37:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1CE2F2859A for ; Mon, 18 Dec 2017 14:37:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 11BAB28C86; Mon, 18 Dec 2017 14:37:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A29CC2866F for ; Mon, 18 Dec 2017 14:37:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758887AbdLROhJ (ORCPT ); Mon, 18 Dec 2017 09:37:09 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:54053 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758796AbdLROgs (ORCPT ); Mon, 18 Dec 2017 09:36:48 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id AE447203A1; Mon, 18 Dec 2017 15:36:46 +0100 (CET) Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 43BA1203A1; Mon, 18 Dec 2017 15:36:46 +0100 (CET) From: Miquel Raynal To: Zhang Rui , Eduardo Valentin , Rob Herring , Mark Rutland , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Catalin Marinas , Will Deacon Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Miquel Raynal , Baruch Siach , David Sniatkiwicz Subject: [PATCH v4 01/12] dt-bindings: thermal: Describe Armada AP806 and CP110 Date: Mon, 18 Dec 2017 15:36:32 +0100 Message-Id: <20171218143643.7714-2-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171218143643.7714-1-miquel.raynal@free-electrons.com> References: <20171218143643.7714-1-miquel.raynal@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Baruch Siach Add compatible strings for AP806 and CP110 that are part of the Armada 8k/7k line of SoCs. Add a note on the differences in the size of the control area in different bindings. This is an existing difference between the Armada 375 binding and the other boards already supported. The new AP806 and CP110 bindings are similar to the existing Armada 375 in this regard. Signed-off-by: Baruch Siach [: reword, additional details] Signed-off-by: Miquel Raynal --- .../devicetree/bindings/thermal/armada-thermal.txt | 24 +++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt index 24aacf8948c5..9b7b2c03cc6f 100644 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt @@ -7,17 +7,31 @@ Required properties: marvell,armada375-thermal marvell,armada380-thermal marvell,armadaxp-thermal + marvell,armada-ap806-thermal + marvell,armada-cp110-thermal - reg: Device's register space. Two entries are expected, see the examples below. - The first one is required for the sensor register; - the second one is required for the control register - to be used for sensor initialization (a.k.a. calibration). + The first one points to the status register (4B). + The second one points to the control registers (8B). + Note: with legacy bindings, the second entry pointed + only to the so called "control MSB" ("control 1"), was + 4B wide and did not let the possibility to reach the + "control LSB" ("control 0") register. This is only + allowed for compatibility reasons in Armada + 370/375/38x/XP DT nodes. -Example: +Examples: + /* Legacy bindings */ thermal@d0018300 { compatible = "marvell,armada370-thermal"; - reg = <0xd0018300 0x4 + reg = <0xd0018300 0x4 0xd0018304 0x4>; }; + + ap_thermal: thermal@6f8084 { + compatible = "marvell,armada-ap806-thermal"; + reg = <0x6f808C 0x4>, + <0x6f8084 0x8>; + };