From patchwork Fri Dec 22 16:14:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10130873 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C761A6038F for ; Fri, 22 Dec 2017 16:14:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BB8CC29BE2 for ; Fri, 22 Dec 2017 16:14:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AF0342A05D; Fri, 22 Dec 2017 16:14:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 595D629BE2 for ; Fri, 22 Dec 2017 16:14:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755971AbdLVQOl (ORCPT ); Fri, 22 Dec 2017 11:14:41 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:55769 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756449AbdLVQOi (ORCPT ); Fri, 22 Dec 2017 11:14:38 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id E6B9D20950; Fri, 22 Dec 2017 17:14:36 +0100 (CET) Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 72DCE2092B; Fri, 22 Dec 2017 17:14:18 +0100 (CET) From: Miquel Raynal To: Zhang Rui , Eduardo Valentin , Rob Herring , Mark Rutland Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Nadav Haklai , Miquel Raynal , Baruch Siach , David Sniatkiwicz Subject: [PATCH v7 07/11] thermal: armada: Add support for Armada CP110 Date: Fri, 22 Dec 2017 17:14:09 +0100 Message-Id: <20171222161413.20816-8-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171222161413.20816-1-miquel.raynal@free-electrons.com> References: <20171222161413.20816-1-miquel.raynal@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Baruch Siach The CP110 component is integrated in the Armada 8k and 7k lines of processors. Signed-off-by: Baruch Siach [: renamed the register pointers as well as some definitions related to the new register names and simplified the init sequence for Armada 380] Signed-off-by: Miquel Raynal Reviewed-by: Gregory CLEMENT Tested-by: Gregory CLEMENT --- drivers/thermal/armada_thermal.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c index f35289b1cea9..f2eba2a6f1a5 100644 --- a/drivers/thermal/armada_thermal.c +++ b/drivers/thermal/armada_thermal.c @@ -37,7 +37,6 @@ #define A375_UNIT_CONTROL_MASK 0x7 #define A375_READOUT_INVERT BIT(15) #define A375_HW_RESETn BIT(8) -#define A380_HW_RESET BIT(8) /* Legacy bindings */ #define LEGACY_CONTROL_MEM_LEN 0x4 @@ -52,6 +51,10 @@ #define CONTROL0_TSEN_RESET BIT(1) #define CONTROL0_TSEN_ENABLE BIT(2) +/* EXT_TSEN refers to the external temperature sensors, out of the AP */ +#define CONTROL1_EXT_TSEN_SW_RESET BIT(7) +#define CONTROL1_EXT_TSEN_HW_RESETn BIT(8) + struct armada_thermal_data; /* Marvell EBU Thermal Sensor Dev Structure */ @@ -153,12 +156,11 @@ static void armada380_init_sensor(struct platform_device *pdev, { u32 reg = readl_relaxed(priv->control1); - /* Reset hardware once */ - if (!(reg & A380_HW_RESET)) { - reg |= A380_HW_RESET; - writel(reg, priv->control1); - msleep(10); - } + /* Disable the HW/SW reset */ + reg |= CONTROL1_EXT_TSEN_HW_RESETn; + reg &= ~CONTROL1_EXT_TSEN_SW_RESET; + writel(reg, priv->control1); + msleep(10); } static void armada_ap806_init_sensor(struct platform_device *pdev, @@ -277,6 +279,19 @@ static const struct armada_thermal_data armada_ap806_data = { .needs_control0 = true, }; +static const struct armada_thermal_data armada_cp110_data = { + .is_valid = armada_is_valid, + .init_sensor = armada380_init_sensor, + .is_valid_bit = BIT(10), + .temp_shift = 0, + .temp_mask = 0x3ff, + .coef_b = 1172499100ULL, + .coef_m = 2000096ULL, + .coef_div = 4201, + .inverted = true, + .needs_control0 = true, +}; + static const struct of_device_id armada_thermal_id_table[] = { { .compatible = "marvell,armadaxp-thermal", @@ -299,6 +314,10 @@ static const struct of_device_id armada_thermal_id_table[] = { .data = &armada_ap806_data, }, { + .compatible = "marvell,armada-cp110-thermal", + .data = &armada_cp110_data, + }, + { /* sentinel */ }, };