From patchwork Mon Jul 16 14:41:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10526935 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D31AE60348 for ; Mon, 16 Jul 2018 14:42:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B9D821FFE6 for ; Mon, 16 Jul 2018 14:42:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AD694274D0; Mon, 16 Jul 2018 14:42:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 584A01FFE6 for ; Mon, 16 Jul 2018 14:42:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729615AbeGPPKJ (ORCPT ); Mon, 16 Jul 2018 11:10:09 -0400 Received: from mail.bootlin.com ([62.4.15.54]:36531 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727452AbeGPPKJ (ORCPT ); Mon, 16 Jul 2018 11:10:09 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 252B4207AB; Mon, 16 Jul 2018 16:42:23 +0200 (CEST) Received: from localhost.localdomain (AAubervilliers-681-1-27-161.w90-88.abo.wanadoo.fr [90.88.147.161]) by mail.bootlin.com (Postfix) with ESMTPSA id B3A6220908; Mon, 16 Jul 2018 16:42:12 +0200 (CEST) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Zhang Rui , Eduardo Valentin Cc: Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Antoine Tenart , Maxime Chevallier , Nadav Haklai , David Sniatkiwicz , Miquel Raynal Subject: [PATCH v3 15/23] dt-bindings: cp110: prepare the syscon file to list other syscons nodes Date: Mon, 16 Jul 2018 16:41:58 +0200 Message-Id: <20180716144206.30985-16-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180716144206.30985-1-miquel.raynal@bootlin.com> References: <20180716144206.30985-1-miquel.raynal@bootlin.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are multiple system controllers in CP110. Because all syscon nodes use the same compatible, it is pertinent to use this same file to list IPs inside it. Thus, change the header to be more generic, and align with AP806 file. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring --- .../bindings/arm/marvell/cp110-system-controller.txt | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt index 29cdbae6c5ac..56e7fb1153e7 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt @@ -1,15 +1,15 @@ -Marvell Armada CP110 System Controller 0 -======================================== +Marvell Armada CP110 System Controller +====================================== The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K -SoCs. It contains two sets of system control registers, System -Controller 0 and System Controller 1. This Device Tree binding allows -to describe the first system controller, which provides registers to -configure various aspects of the SoC. +SoCs. It contains system controllers, which provide several registers +giving access to numerous features: clocks, pin-muxing and many other +SoC configuration items. This DT binding allows to describe these +system controllers. For the top level node: - compatible: must be: "syscon", "simple-mfd"; - - reg: register area of the CP110 system controller 0 + - reg: register area of the CP110 system controller Clocks: -------