From patchwork Wed Aug 8 22:47:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10560597 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4EBEA90E3 for ; Wed, 8 Aug 2018 22:47:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3EBD22ABBD for ; Wed, 8 Aug 2018 22:47:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 31AF32AC82; Wed, 8 Aug 2018 22:47:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C9F462ABBD for ; Wed, 8 Aug 2018 22:47:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731148AbeHIBIy (ORCPT ); Wed, 8 Aug 2018 21:08:54 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:40146 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727530AbeHIBIy (ORCPT ); Wed, 8 Aug 2018 21:08:54 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CB34860B83; Wed, 8 Aug 2018 22:47:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533768426; bh=5eMxLBYZ6r4xQ2IlCxor4b5evj8/8y7+VWD3Bq1S/Pk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mtuHfUeVH2W6C1J50ux76flvM2akIXwfi6FfAi3zKnTX/bnOTSqJTipUVjljnVc4S 97VFi44fwV8571FqZ6P0YtTmfnJFbdnzdBDg3Y9s45ugoiY18o0kE0upOlreUn9sS/ qnVKSlfuH1T/h3ZIaI7PZFr9o/pTm4yIF4sbfLYM= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 51FED60B22; Wed, 8 Aug 2018 22:47:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533768426; bh=5eMxLBYZ6r4xQ2IlCxor4b5evj8/8y7+VWD3Bq1S/Pk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mtuHfUeVH2W6C1J50ux76flvM2akIXwfi6FfAi3zKnTX/bnOTSqJTipUVjljnVc4S 97VFi44fwV8571FqZ6P0YtTmfnJFbdnzdBDg3Y9s45ugoiY18o0kE0upOlreUn9sS/ qnVKSlfuH1T/h3ZIaI7PZFr9o/pTm4yIF4sbfLYM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 51FED60B22 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, hoegsberg@gmail.com, nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, sboyd@kernel.org, vireshk@kernel.org, linux-arm-kernel@lists.infradead.org, sibis@codeaurora.org Subject: [PATCH 1/2] dt-bindings: Document qcom,adreno-gmu Date: Wed, 8 Aug 2018 16:47:00 -0600 Message-Id: <20180808224701.7527-2-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180808224701.7527-1-jcrouse@codeaurora.org> References: <20180808224701.7527-1-jcrouse@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Document the device tree bindings for the Adreno GMU device available on Adreno a6xx targets. Reviewed-by: Rob Herring Signed-off-by: Jordan Crouse --- .../devicetree/bindings/display/msm/gmu.txt | 54 +++++++++++++++++++ .../devicetree/bindings/display/msm/gpu.txt | 10 +++- 2 files changed, 62 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt new file mode 100644 index 000000000000..6ab3e2cf29e9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt @@ -0,0 +1,54 @@ +Qualcomm adreno/snapdragon GMU (Graphics management unit) + +The GMU is a programmable power controller for the GPU. the CPU controls the +GMU which in turn handles power controls for the GPU. + +Required properties: +- compatible: + * "qcom,adreno-gmu" +- reg: Physical base address and length of the GMU registers. +- reg-names: Matching names for the register regions + * "gmu" + * "gmu_pdc" +- interrupts: The interrupt signals from the GMU. +- interrupt-names: Matching names for the interrupts + * "hfi" + * "gmu" +- clocks: phandles to the device clocks +- clock-names: Matching names for the clocks + * "gmu" + * "cxo" + * "axi" + * "mnoc" +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> +- iommus: phandle to the adreno iommu +- operating-points-v2: phandle to the OPP operating points + +Example: + +/ { + ... + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb200000 0x300000>; + reg-names = "gmu", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&clock_gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + }; +}; diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 43fac0fe09bb..544a7510166b 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -8,12 +8,18 @@ Required properties: with the chip-id. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the gpu. -- clocks: device clocks + +Optional properties. +- clocks: device clocks. Required for a3xx, a4xx and a5xx targets. a6xx and + newer with a GMU attached do not have direct clock control from the CPU and + do not need to provide clock properties. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required: +- clock-names: the following clocks can be provided: * "core" * "iface" * "mem_iface" +- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will + control the power for the GPU Example: