From patchwork Mon Aug 27 15:11:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10577311 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6FE9714BD for ; Mon, 27 Aug 2018 15:11:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5F11429C92 for ; Mon, 27 Aug 2018 15:11:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5364529D53; Mon, 27 Aug 2018 15:11:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CB42C29C92 for ; Mon, 27 Aug 2018 15:11:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727136AbeH0S6j (ORCPT ); Mon, 27 Aug 2018 14:58:39 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:36070 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726920AbeH0S6j (ORCPT ); Mon, 27 Aug 2018 14:58:39 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E374E60BDE; Mon, 27 Aug 2018 15:11:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1535382697; bh=208kDU9Yfd6/fIeNRIjlF714MQg0uKaPSR2o75tN30M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F9R0eDjwCOOrES7Whtjqv6kqcpofL8GU7j7JEqnNzWi4mABfJM5MYpSlh2Gx6wu8E RWghUiicpyoTDcPdCK9TUJRRbloMK2z2KvbTuDwJidQJV1fc5GKuHqLswMfVeRJ3qL hmWHqIAmGN2zyA+Qt67U8ek71eC5uv2dSeVQAZ4o= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 209316076A; Mon, 27 Aug 2018 15:11:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1535382688; bh=208kDU9Yfd6/fIeNRIjlF714MQg0uKaPSR2o75tN30M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QVJWStNCQaEHePU5nIK+ZcB+2IyHPPSsH78Qt6xCjZuqn3i4yvyHPOPUhE9+e6MJF jsTQLxk3tw8tjZ65t/cEr41h7Uz5jkyHsdqQenJ0GcdMuVLd2OVJxfsVG5JW2tZsOM RaULoVi73ikRHQ/EO/IrLnnRo9gZ7eVxTeinR3Uk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 209316076A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, georgi.djakov@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, bjorn.andersson@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, vireshk@kernel.org, nm@ti.com, sboyd@kernel.org Subject: [PATCH 8/9] drm/msm/a6xx: Add support for an interconnect path Date: Mon, 27 Aug 2018 09:11:11 -0600 Message-Id: <20180827151112.25211-9-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180827151112.25211-1-jcrouse@codeaurora.org> References: <20180827151112.25211-1-jcrouse@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for setting the OPP defined bandwidth for a given GPU frequency value for a6xx. On sdm845 even though the GPU frequency is set by the GMU but the bus bandwidth quota is set by the CPU. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 27 +++++++++++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 7 +++++++ drivers/gpu/drm/msm/msm_gpu.h | 3 +++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index d0dac4c2e3e7..d63eefc7c74d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include "a6xx_gpu.h" @@ -65,8 +66,15 @@ static bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); } -static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) +static void a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) { + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; + struct dev_pm_opp *opp; + u64 ab, ib; + int ret; + gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, @@ -82,7 +90,22 @@ static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); - return gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); + ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); + if (ret) + dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); + + /* Set the interconnect bandwidth from the CPU */ + if (IS_ERR_OR_NULL(gpu->icc_path)) + return; + + opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, + gmu->gpu_freqs[index], true); + if (!IS_ERR_OR_NULL(opp)) { + if (!dev_pm_opp_get_interconnect_bw(opp, "port0", &ab, &ib)) + icc_set(gpu->icc_path, ab, ib); + + dev_pm_opp_put(opp); + } } static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index da1363a0c54d..2eace9bf32c7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "adreno_gpu.h" #include "msm_gem.h" #include "msm_mmu.h" @@ -694,6 +695,9 @@ static int adreno_get_pwrlevels(struct device *dev, DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); + /* Check for an interconnect path for the bus */ + gpu->icc_path = of_icc_get(dev, "port0"); + return 0; } @@ -732,10 +736,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) { + struct msm_gpu *gpu = &adreno_gpu->base; unsigned int i; for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) release_firmware(adreno_gpu->fw[i]); + icc_put(gpu->icc_path); + msm_gpu_cleanup(&adreno_gpu->base); } diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 9122ee6e55e4..9c851d03f344 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -20,6 +20,7 @@ #include #include +#include #include "msm_drv.h" #include "msm_fence.h" @@ -117,6 +118,8 @@ struct msm_gpu { struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; uint32_t fast_rate; + struct icc_path *icc_path; + /* Hang and Inactivity Detection: */ #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */