From patchwork Thu Jun 27 12:52:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11019657 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9AC551708 for ; Thu, 27 Jun 2019 12:52:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E20A28A59 for ; Thu, 27 Jun 2019 12:52:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8247B28A71; Thu, 27 Jun 2019 12:52:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 36DB428A81 for ; Thu, 27 Jun 2019 12:52:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727089AbfF0Mwv (ORCPT ); Thu, 27 Jun 2019 08:52:51 -0400 Received: from relay4-d.mail.gandi.net ([217.70.183.196]:34535 "EHLO relay4-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726653AbfF0Mwu (ORCPT ); Thu, 27 Jun 2019 08:52:50 -0400 X-Originating-IP: 86.250.200.211 Received: from localhost.localdomain (lfbn-1-17395-211.w86-250.abo.wanadoo.fr [86.250.200.211]) (Authenticated sender: miquel.raynal@bootlin.com) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 56969E000E; Thu, 27 Jun 2019 12:52:48 +0000 (UTC) From: Miquel Raynal To: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Gregory Clement , Maxime Chevallier , Nadav Haklai , Bjorn Helgaas , "Rafael J . Wysocki" , linux-pm@vger.kernel.org, =?utf-8?q?Marek_Beh=C3=BAn?= , Miquel Raynal Subject: [PATCH v3 1/4] clk: mvebu: armada-37xx-periph: add PCIe gated clock Date: Thu, 27 Jun 2019 14:52:42 +0200 Message-Id: <20190627125245.26788-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190627125245.26788-1-miquel.raynal@bootlin.com> References: <20190627125245.26788-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PCIe clock is a gated clock which has the same source as GbE0 (both IPs share a set of registers). This source clock is called 'gbe_core' in the driver. Signed-off-by: Miquel Raynal --- drivers/clk/mvebu/armada-37xx-periph.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 4c20093a42fb..1e18c5a875bd 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -304,6 +304,7 @@ PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1); PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6); PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12); PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18); +static PERIPH_GATE(pcie, 14); static struct clk_periph_data data_sb[] = { REF_CLK_MUX_DD(gbe_50), @@ -319,6 +320,7 @@ static struct clk_periph_data data_sb[] = { REF_CLK_FULL_DD(sdio), REF_CLK_FULL_DD(usb32_usb2_sys), REF_CLK_FULL_DD(usb32_ss_sys), + REF_CLK_GATE(pcie, "gbe_core"), { }, };