From patchwork Thu Jul 4 09:13:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 11031295 X-Patchwork-Delegate: rui.zhang@intel.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4C6C1510 for ; Thu, 4 Jul 2019 09:22:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D3C83286B3 for ; Thu, 4 Jul 2019 09:22:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C717128727; Thu, 4 Jul 2019 09:22:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 497B5286B3 for ; Thu, 4 Jul 2019 09:22:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727452AbfGDJWn (ORCPT ); Thu, 4 Jul 2019 05:22:43 -0400 Received: from inva020.nxp.com ([92.121.34.13]:47950 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727147AbfGDJWm (ORCPT ); Thu, 4 Jul 2019 05:22:42 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 715961A0588; Thu, 4 Jul 2019 11:22:39 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 60AEB1A0587; Thu, 4 Jul 2019 11:22:24 +0200 (CEST) Received: from titan.ap.freescale.net (TITAN.ap.freescale.net [10.192.208.233]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 908CC40299; Thu, 4 Jul 2019 17:22:10 +0800 (SGT) From: Anson.Huang@nxp.com To: rui.zhang@intel.com, edubezval@gmail.com, daniel.lezcano@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, catalin.marinas@arm.com, will@kernel.org, leonard.crestez@nxp.com, daniel.baluta@nxp.com, ping.bai@nxp.com, olof@lixom.net, maxime.ripard@bootlin.com, jagan@amarulasolutions.com, bjorn.andersson@linaro.org, dinguyen@kernel.org, enric.balletbo@collabora.com, marcin.juszkiewicz@linaro.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH 2/4] thermal: imx8mm: Add support for i.MX8MM thermal monitoring unit Date: Thu, 4 Jul 2019 17:13:11 +0800 Message-Id: <20190704091313.9516-3-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20190704091313.9516-1-Anson.Huang@nxp.com> References: <20190704091313.9516-1-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Anson Huang i.MX8MM has a thermal monitoring unit(TMU) inside, it ONLY has one sensor for CPU, add support for reading immediate temperature of this sensor. Signed-off-by: Anson Huang --- drivers/thermal/Kconfig | 10 +++ drivers/thermal/Makefile | 1 + drivers/thermal/imx8mm_thermal.c | 134 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 145 insertions(+) create mode 100644 drivers/thermal/imx8mm_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 454cbe5..d1663cd 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -244,6 +244,16 @@ config IMX_SC_THERMAL sensor. It supports one critical trip point and one passive trip point for each thermal sensor. +config IMX8MM_THERMAL + tristate "Temperature sensor driver for Freescale i.MX8MM SoC" + depends on ARCH_MXC + depends on OF + help + Support for Thermal Monitoring Unit (TMU) found on Freescale i.MX8MM SoC. + It supports one critical trip point and one passive trip point. The + cpufreq is used as the cooling device to throttle CPUs when the passive + trip is crossed. + config MAX77620_THERMAL tristate "Temperature sensor driver for Maxim MAX77620 PMIC" depends on MFD_MAX77620 diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 717a1ba..a397d4d 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o obj-$(CONFIG_TANGO_THERMAL) += tango_thermal.o obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o obj-$(CONFIG_IMX_SC_THERMAL) += imx_sc_thermal.o +obj-$(CONFIG_IMX8MM_THERMAL) += imx8mm_thermal.o obj-$(CONFIG_MAX77620_THERMAL) += max77620_thermal.o obj-$(CONFIG_QORIQ_THERMAL) += qoriq_thermal.o obj-$(CONFIG_DA9062_THERMAL) += da9062-thermal.o diff --git a/drivers/thermal/imx8mm_thermal.c b/drivers/thermal/imx8mm_thermal.c new file mode 100644 index 0000000..04f8a8f --- /dev/null +++ b/drivers/thermal/imx8mm_thermal.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "thermal_core.h" + +#define TER 0x0 /* TMU enable */ +#define TRITSR 0x20 /* TMU immediate temp */ + +#define TER_EN BIT(31) +#define TRITSR_VAL_MASK 0xff + +#define TEMP_LOW_LIMIT 10 + +struct imx8mm_tmu { + struct thermal_zone_device *tzd; + void __iomem *base; + struct clk *clk; +}; + +static int tmu_get_temp(void *data, int *temp) +{ + struct imx8mm_tmu *tmu = data; + u32 val; + + /* the temp sensor need about 1ms to finish the measurement */ + usleep_range(1000, 2000); + + val = readl_relaxed(tmu->base + TRITSR) & TRITSR_VAL_MASK; + if (val < TEMP_LOW_LIMIT) + return -EAGAIN; + + *temp = val * 1000; + + return 0; +} + +static struct thermal_zone_of_device_ops tmu_tz_ops = { + .get_temp = tmu_get_temp, +}; + +static int imx8mm_tmu_probe(struct platform_device *pdev) +{ + struct imx8mm_tmu *tmu; + u32 val; + int ret; + + tmu = devm_kzalloc(&pdev->dev, sizeof(struct imx8mm_tmu), GFP_KERNEL); + if (!tmu) + return -ENOMEM; + + tmu->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tmu->base)) + return PTR_ERR(tmu->base); + + tmu->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(tmu->clk)) { + ret = PTR_ERR(tmu->clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, + "failed to get tmu clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(tmu->clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable tmu clock: %d\n", ret); + return ret; + } + + tmu->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, + tmu, &tmu_tz_ops); + if (IS_ERR(tmu->tzd)) { + dev_err(&pdev->dev, + "failed to register thermal zone sensor: %d\n", ret); + return PTR_ERR(tmu->tzd); + } + + platform_set_drvdata(pdev, tmu); + + /* enable the monitor */ + val = readl_relaxed(tmu->base + TER); + val |= TER_EN; + writel_relaxed(val, tmu->base + TER); + + return 0; +} + +static int imx8mm_tmu_remove(struct platform_device *pdev) +{ + struct imx8mm_tmu *tmu = platform_get_drvdata(pdev); + u32 val; + + /* disable TMU */ + val = readl_relaxed(tmu->base + TER); + val &= ~TER_EN; + writel_relaxed(val, tmu->base + TER); + + clk_disable_unprepare(tmu->clk); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static const struct of_device_id imx8mm_tmu_table[] = { + { .compatible = "fsl,imx8mm-tmu", }, + { }, +}; + +static struct platform_driver imx8mm_tmu = { + .driver = { + .name = "i.mx8mm_thermal", + .of_match_table = imx8mm_tmu_table, + }, + .probe = imx8mm_tmu_probe, + .remove = imx8mm_tmu_remove, +}; +module_platform_driver(imx8mm_tmu); + +MODULE_AUTHOR("Anson Huang "); +MODULE_DESCRIPTION("i.MX8MM Thermal Monitor Unit driver"); +MODULE_LICENSE("GPL v2");