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Mon, 22 Jul 2019 09:47:24 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, gregkh@linuxfoundation.org, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v12 2/9] dt-bindings: ddr: add LPDDR3 memories Date: Mon, 22 Jul 2019 11:46:39 +0200 Message-Id: <20190722094646.13342-3-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190722094646.13342-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSf0yMcRzHfe/5Wet4XNQnwlzYMVLJ9h1WDNszW83or9I4PCvTHe6pJDYX q0inaOMmpbTUrkvKqTSKarIuXTeNdPIrltKPURpTpqcn/Pf6vj/v9/uzffZlCdUItYA9pI8X DHptnJp2J6uf/HSs8U9bHx2Q0hGIK80VFH451kfhG83tFC772ovw2aIKGue05ilw2wUdzur9 QmCH4w6Dn50ZZHC30Rd/zXxD4ed112k8ampG2OyoV+Dy5h4GF790KrCzdTt2pZTSOPVhM4Ob BtMp/PtFJYkbOndg16/ZePzpB7TZh7fmWxE//v0yyY90pTJ8rtFJ8vev9TB8leU8zTfkWRne dHaY5h8PP1DwF20WxN+1n+RHqxbv9Ih033RQiDuUKBjWhuxzjzWZ7fTRyhVJkwMTjBG9XZyB 3FjggqGzrp+WWMWVInjV4ZeB3Kd4DEF7SgmSH6MIfrW7qL+Jbz+zFfKgBEH9j27yX+RRV+tU hGVpzh9qLcekwDzOjCD3827JQ3DvCbhYfh1JA08uBMqemKd3k9xySH+Yzkis5ELBOnGJlLct gbI7jwip043bDP0tOqkHuEIWPrmKKUkHbhtkN4bKdk8YaLExMvuCPSdzpkYEo6kQyXwKerPy ZjwboanFOV1DcCuhom6tLG8Bl22clNtnQ9fQXEkmpvBy9VVClpVwLk0luzVgy+xQyOwFJdYr M+U8PG/LoOXj5CBoKh+jstGSa/+XFSBkQd5CgqiLEcR1euG4v6jViQn6GP8DR3RVaOob2n+3 fK9F9RP7GxHHIrWHMqA6OFpFaRPFE7pGBCyhnqfUB6yPVikPak8kC4Yjew0JcYLYiBaypNpb eXLWuygVF6ONFw4LwlHB8HeqYN0WGNEGTZtT3FOwetAa6905XJMdUBjZWxzuczt8u6Nrcnnp R6+thkuaqiSN7675mtOeYetSJ7NC88PYhLIIYVFl7bZEi/CM8SmZsObes6b5Zby2B5lsDRWR SR5FgX3LYuNrLN+KUFHPrX0paRFzkoGKGr06HEXMXarVjRRcCBq6qQxUk2KsNnAVYRC1fwBS Wun+ggMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMIsWRmVeSWpSXmKPExsVy+t/xe7q6baaxBrun6FtsnLGe1eL6l+es FvOPnGO1WP3xMaNF8+L1bBaTT81lsjjTnWvR//g1s8X58xvYLc42vWG3uNUgY/Gx5x6rxeVd c9gsPvceYbSYcX4fk8XaI3fZLZZev8hkcfGUq8XtxhVsFq17j7BbHH7Tzmrx79pGFov9V7ws bv/ms/h24hGjg6THmnlrGD2+fZ3E4vH+Riu7x+yGiyweO2fdZffYtKqTzWP/3DXsHr3N79g8 Dr7bw+TRt2UVo8fm09UenzfJBfBE6dkU5ZeWpCpk5BeX2CpFG1oY6RlaWugZmVjqGRqbx1oZ mSrp29mkpOZklqUW6dsl6GX0zjjNVrBRreLvqz/sDYz35boYOTkkBEwkPv2cwARiCwksZZS4 MC0SIi4mMWnfdnYIW1jiz7Uuti5GLqCaT4wSr460MHcxcnCwCehJ7FhVCBIXEZjDKPGzaxsj iMMs8JtZ4uDdfrBuYQE7idXHZrCB2CwCqhLte9vB4rwC9hJr/kxkgdggL7F6wwGwoZwCDhIv j+dCHGQvsf/FdsYJjHwLGBlWMYqklhbnpucWG+kVJ+YWl+al6yXn525iBEbotmM/t+xg7HoX fIhRgINRiYf3xmaTWCHWxLLiytxDjBIczEoivHkGprFCvCmJlVWpRfnxRaU5qcWHGE2BbprI LCWanA9MHnkl8YamhuYWlobmxubGZhZK4rwdAgdjhATSE0tSs1NTC1KLYPqYODilGhjDHLt1 1yzoZKnk/i2mw6/wYOGxcy9LFLlzlm7beEKrJCMyMHuBsttTn+onFy4c7NrcWr95y7mKdw0H pt5+qpKsM3PJtfey9x9dlexW2vC/44ePZcHD9X2CzOfYFubx7ONgz10dI5Qp67x1YYzHvI0Z Jmm79v58Kua/wPjXNH4tmweSRxZI7FJSYinOSDTUYi4qTgQA95o6vuYCAAA= X-CMS-MailID: 20190722094726eucas1p2471055ae10f65df44fa1e640491e528f X-Msg-Generator: CA X-RootMTR: 20190722094726eucas1p2471055ae10f65df44fa1e640491e528f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190722094726eucas1p2471055ae10f65df44fa1e640491e528f References: <20190722094646.13342-1-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Specifies the AC timing parameters of the LPDDR3 memory device. Reviewed-by: Rob Herring Signed-off-by: Lukasz Luba --- .../bindings/ddr/lpddr3-timings.txt | 58 +++++++++++ .../devicetree/bindings/ddr/lpddr3.txt | 97 +++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3-timings.txt create mode 100644 Documentation/devicetree/bindings/ddr/lpddr3.txt diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt new file mode 100644 index 000000000000..84705e50a3fd --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt @@ -0,0 +1,58 @@ +* AC timing parameters of LPDDR3 memories for a given speed-bin. + +The structures are based on LPDDR2 and extended where needed. + +Required properties: +- compatible : Should be "jedec,lpddr3-timings" +- min-freq : minimum DDR clock frequency for the speed-bin. Type is +- reg : maximum DDR clock frequency for the speed-bin. Type is + +Optional properties: + +The following properties represent AC timing parameters from the memory +data-sheet of the device for a given speed-bin. All these properties are +of type and the default unit is ps (pico seconds). +- tRFC +- tRRD +- tRPab +- tRPpb +- tRCD +- tRC +- tRAS +- tWTR +- tWR +- tRTP +- tW2W-C2C +- tR2R-C2C +- tFAW +- tXSR +- tXP +- tCKE +- tCKESR +- tMRD + +Example: + +timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; +}; diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt new file mode 100644 index 000000000000..3b2485b84b3f --- /dev/null +++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt @@ -0,0 +1,97 @@ +* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C + +Required properties: +- compatible : Should be - "jedec,lpddr3" +- density : representing density in Mb (Mega bits) +- io-width : representing bus width. Possible values are 8, 16, 32, 64 +- #address-cells: Must be set to 1 +- #size-cells: Must be set to 0 + +Optional properties: + +The following optional properties represent the minimum value of some AC +timing parameters of the DDR device in terms of number of clock cycles. +These values shall be obtained from the device data-sheet. +- tRFC-min-tck +- tRRD-min-tck +- tRPab-min-tck +- tRPpb-min-tck +- tRCD-min-tck +- tRC-min-tck +- tRAS-min-tck +- tWTR-min-tck +- tWR-min-tck +- tRTP-min-tck +- tW2W-C2C-min-tck +- tR2R-C2C-min-tck +- tWL-min-tck +- tDQSCK-min-tck +- tRL-min-tck +- tFAW-min-tck +- tXSR-min-tck +- tXP-min-tck +- tCKE-min-tck +- tCKESR-min-tck +- tMRD-min-tck + +Child nodes: +- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". + "lpddr3-timings" provides AC timing parameters of the device for + a given speed-bin. Please see Documentation/devicetree/ + bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" + +Example: + +samsung_K3QF2F20DB: lpddr3 { + compatible = "Samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + #address-cells = <1>; + #size-cells = <0>; + + tRFC-min-tck = <17>; + tRRD-min-tck = <2>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRCD-min-tck = <3>; + tRC-min-tck = <6>; + tRAS-min-tck = <5>; + tWTR-min-tck = <2>; + tWR-min-tck = <7>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tR2R-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tDQSCK-min-tck = <5>; + tRL-min-tck = <14>; + tFAW-min-tck = <5>; + tXSR-min-tck = <12>; + tXP-min-tck = <2>; + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tMRD-min-tck = <5>; + + timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + compatible = "jedec,lpddr3-timings"; + reg = <800000000>; /* workaround: it shows max-freq */ + min-freq = <100000000>; + tRFC = <65000>; + tRRD = <6000>; + tRPab = <12000>; + tRPpb = <12000>; + tRCD = <10000>; + tRC = <33750>; + tRAS = <23000>; + tWTR = <3750>; + tWR = <7500>; + tRTP = <3750>; + tW2W-C2C = <0>; + tR2R-C2C = <0>; + tFAW = <25000>; + tXSR = <70000>; + tXP = <3750>; + tCKE = <3750>; + tCKESR = <3750>; + tMRD = <7000>; + }; +}