| Message ID | 20190925161813.21117-2-l.luba@partner.samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Exynos5 DMC interrupt mode | expand |
On Wed, Sep 25, 2019 at 06:18:11PM +0200, Lukasz Luba wrote: > Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid > XU3-family boards. It will be used instead of devfreq polling mode > governor. The interrupt is connected to performance counters private > for DMC, which might track utilisation of the memory channels. > > Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> > --- > arch/arm/boot/dts/exynos5420.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi > index ac49373baae7..72738e620d11 100644 > --- a/arch/arm/boot/dts/exynos5420.dtsi > +++ b/arch/arm/boot/dts/exynos5420.dtsi > @@ -240,6 +240,8 @@ > dmc: memory-controller@10c20000 { > compatible = "samsung,exynos5422-dmc"; > reg = <0x10c20000 0x100>, <0x10c30000 0x100>; > + interrupt-parent = <&combiner>; > + interrupts = <16 0>; You register DMC for DREX0 and DREX1 but take only DREX0 interrupt. Why skipping second? Best regards, Krzysztof > clocks = <&clock CLK_FOUT_SPLL>, > <&clock CLK_MOUT_SCLK_SPLL>, > <&clock CLK_FF_DOUT_SPLL2>, > -- > 2.17.1 >
Hi Krzysztof, On 9/27/19 10:53 AM, Krzysztof Kozlowski wrote: > On Wed, Sep 25, 2019 at 06:18:11PM +0200, Lukasz Luba wrote: >> Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid >> XU3-family boards. It will be used instead of devfreq polling mode >> governor. The interrupt is connected to performance counters private >> for DMC, which might track utilisation of the memory channels. >> >> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> >> --- >> arch/arm/boot/dts/exynos5420.dtsi | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi >> index ac49373baae7..72738e620d11 100644 >> --- a/arch/arm/boot/dts/exynos5420.dtsi >> +++ b/arch/arm/boot/dts/exynos5420.dtsi >> @@ -240,6 +240,8 @@ >> dmc: memory-controller@10c20000 { >> compatible = "samsung,exynos5422-dmc"; >> reg = <0x10c20000 0x100>, <0x10c30000 0x100>; >> + interrupt-parent = <&combiner>; >> + interrupts = <16 0>; > > You register DMC for DREX0 and DREX1 but take only DREX0 interrupt. Why > skipping second? > Right, the second should also be there: <16 1>. The channel 1 has not been triggered in CPU test cases but might be used by some other NoC clients. I will add it in the next version. Regards, Lukasz
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index ac49373baae7..72738e620d11 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -240,6 +240,8 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + interrupt-parent = <&combiner>; + interrupts = <16 0>; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>,
Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid XU3-family boards. It will be used instead of devfreq polling mode governor. The interrupt is connected to performance counters private for DMC, which might track utilisation of the memory channels. Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> --- arch/arm/boot/dts/exynos5420.dtsi | 2 ++ 1 file changed, 2 insertions(+)