| Message ID | 20191128014016.4389-2-sean.j.christopherson@intel.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | x86/cpu: Clean up handling of VMX features | expand |
Hi Sean,
I love your patch! Yet something to improve:
[auto build test ERROR on tip/auto-latest]
[also build test ERROR on next-20191128]
[cannot apply to tip/x86/core kvm/linux-next v5.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Sean-Christopherson/x86-cpu-Clean-up-handling-of-VMX-features/20191128-094556
base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git e445033e58108a9891abfbc0dea90b066a75e4a9
config: i386-randconfig-a002-20191128 (attached as .config)
compiler: gcc-6 (Debian 6.3.0-18+deb9u1) 6.3.0 20170516
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from arch/x86/include/asm/processor.h:22:0,
from arch/x86/include/asm/cpufeature.h:5,
from arch/x86/include/asm/thread_info.h:53,
from include/linux/thread_info.h:38,
from arch/x86/include/asm/preempt.h:7,
from include/linux/preempt.h:78,
from include/linux/percpu.h:6,
from include/linux/cpuidle.h:14,
from drivers//idle/intel_idle.c:45:
drivers//idle/intel_idle.c: In function 'sklh_idle_state_table_update':
>> drivers//idle/intel_idle.c:1287:10: error: 'MSR_IA32_FEATURE_CONTROL' undeclared (first use in this function)
rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
^
arch/x86/include/asm/msr.h:279:28: note: in definition of macro 'rdmsrl'
((val) = native_read_msr((msr)))
^~~
drivers//idle/intel_idle.c:1287:10: note: each undeclared identifier is reported only once for each function it appears in
rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
^
arch/x86/include/asm/msr.h:279:28: note: in definition of macro 'rdmsrl'
((val) = native_read_msr((msr)))
^~~
vim +/MSR_IA32_FEATURE_CONTROL +1287 drivers//idle/intel_idle.c
5dcef694860100 Len Brown 2016-04-06 1189
5dcef694860100 Len Brown 2016-04-06 1190 /*
5dcef694860100 Len Brown 2016-04-06 1191 * Translate IRTL (Interrupt Response Time Limit) MSR to usec
5dcef694860100 Len Brown 2016-04-06 1192 */
5dcef694860100 Len Brown 2016-04-06 1193
5dcef694860100 Len Brown 2016-04-06 1194 static unsigned int irtl_ns_units[] = {
5dcef694860100 Len Brown 2016-04-06 1195 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
5dcef694860100 Len Brown 2016-04-06 1196
5dcef694860100 Len Brown 2016-04-06 1197 static unsigned long long irtl_2_usec(unsigned long long irtl)
5dcef694860100 Len Brown 2016-04-06 1198 {
5dcef694860100 Len Brown 2016-04-06 1199 unsigned long long ns;
5dcef694860100 Len Brown 2016-04-06 1200
3451ab3ebf92b1 Jan Beulich 2016-06-27 1201 if (!irtl)
3451ab3ebf92b1 Jan Beulich 2016-06-27 1202 return 0;
3451ab3ebf92b1 Jan Beulich 2016-06-27 1203
bef450962597ff Jan Beulich 2016-06-27 1204 ns = irtl_ns_units[(irtl >> 10) & 0x7];
5dcef694860100 Len Brown 2016-04-06 1205
5dcef694860100 Len Brown 2016-04-06 1206 return div64_u64((irtl & 0x3FF) * ns, 1000);
5dcef694860100 Len Brown 2016-04-06 1207 }
5dcef694860100 Len Brown 2016-04-06 1208 /*
5dcef694860100 Len Brown 2016-04-06 1209 * bxt_idle_state_table_update(void)
5dcef694860100 Len Brown 2016-04-06 1210 *
5dcef694860100 Len Brown 2016-04-06 1211 * On BXT, we trust the IRTL to show the definitive maximum latency
5dcef694860100 Len Brown 2016-04-06 1212 * We use the same value for target_residency.
5dcef694860100 Len Brown 2016-04-06 1213 */
5dcef694860100 Len Brown 2016-04-06 1214 static void bxt_idle_state_table_update(void)
5dcef694860100 Len Brown 2016-04-06 1215 {
5dcef694860100 Len Brown 2016-04-06 1216 unsigned long long msr;
3451ab3ebf92b1 Jan Beulich 2016-06-27 1217 unsigned int usec;
5dcef694860100 Len Brown 2016-04-06 1218
5dcef694860100 Len Brown 2016-04-06 1219 rdmsrl(MSR_PKGC6_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1220 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1221 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1222 bxt_cstates[2].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1223 bxt_cstates[2].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1224 }
5dcef694860100 Len Brown 2016-04-06 1225
5dcef694860100 Len Brown 2016-04-06 1226 rdmsrl(MSR_PKGC7_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1227 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1228 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1229 bxt_cstates[3].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1230 bxt_cstates[3].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1231 }
5dcef694860100 Len Brown 2016-04-06 1232
5dcef694860100 Len Brown 2016-04-06 1233 rdmsrl(MSR_PKGC8_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1234 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1235 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1236 bxt_cstates[4].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1237 bxt_cstates[4].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1238 }
5dcef694860100 Len Brown 2016-04-06 1239
5dcef694860100 Len Brown 2016-04-06 1240 rdmsrl(MSR_PKGC9_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1241 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1242 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1243 bxt_cstates[5].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1244 bxt_cstates[5].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1245 }
5dcef694860100 Len Brown 2016-04-06 1246
5dcef694860100 Len Brown 2016-04-06 1247 rdmsrl(MSR_PKGC10_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1248 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1249 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1250 bxt_cstates[6].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1251 bxt_cstates[6].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1252 }
5dcef694860100 Len Brown 2016-04-06 1253
5dcef694860100 Len Brown 2016-04-06 1254 }
d70e28f57e14a4 Len Brown 2016-03-13 1255 /*
d70e28f57e14a4 Len Brown 2016-03-13 1256 * sklh_idle_state_table_update(void)
d70e28f57e14a4 Len Brown 2016-03-13 1257 *
d70e28f57e14a4 Len Brown 2016-03-13 1258 * On SKL-H (model 0x5e) disable C8 and C9 if:
d70e28f57e14a4 Len Brown 2016-03-13 1259 * C10 is enabled and SGX disabled
d70e28f57e14a4 Len Brown 2016-03-13 1260 */
d70e28f57e14a4 Len Brown 2016-03-13 1261 static void sklh_idle_state_table_update(void)
d70e28f57e14a4 Len Brown 2016-03-13 1262 {
d70e28f57e14a4 Len Brown 2016-03-13 1263 unsigned long long msr;
d70e28f57e14a4 Len Brown 2016-03-13 1264 unsigned int eax, ebx, ecx, edx;
d70e28f57e14a4 Len Brown 2016-03-13 1265
d70e28f57e14a4 Len Brown 2016-03-13 1266
d70e28f57e14a4 Len Brown 2016-03-13 1267 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
d70e28f57e14a4 Len Brown 2016-03-13 1268 if (max_cstate <= 7)
d70e28f57e14a4 Len Brown 2016-03-13 1269 return;
d70e28f57e14a4 Len Brown 2016-03-13 1270
d70e28f57e14a4 Len Brown 2016-03-13 1271 /* if PC10 not present in CPUID.MWAIT.EDX */
d70e28f57e14a4 Len Brown 2016-03-13 1272 if ((mwait_substates & (0xF << 28)) == 0)
d70e28f57e14a4 Len Brown 2016-03-13 1273 return;
d70e28f57e14a4 Len Brown 2016-03-13 1274
6cfb2374f83bc7 Len Brown 2017-01-07 1275 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
d70e28f57e14a4 Len Brown 2016-03-13 1276
d70e28f57e14a4 Len Brown 2016-03-13 1277 /* PC10 is not enabled in PKG C-state limit */
d70e28f57e14a4 Len Brown 2016-03-13 1278 if ((msr & 0xF) != 8)
d70e28f57e14a4 Len Brown 2016-03-13 1279 return;
d70e28f57e14a4 Len Brown 2016-03-13 1280
d70e28f57e14a4 Len Brown 2016-03-13 1281 ecx = 0;
d70e28f57e14a4 Len Brown 2016-03-13 1282 cpuid(7, &eax, &ebx, &ecx, &edx);
d70e28f57e14a4 Len Brown 2016-03-13 1283
d70e28f57e14a4 Len Brown 2016-03-13 1284 /* if SGX is present */
d70e28f57e14a4 Len Brown 2016-03-13 1285 if (ebx & (1 << 2)) {
d70e28f57e14a4 Len Brown 2016-03-13 1286
d70e28f57e14a4 Len Brown 2016-03-13 @1287 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
d70e28f57e14a4 Len Brown 2016-03-13 1288
d70e28f57e14a4 Len Brown 2016-03-13 1289 /* if SGX is enabled */
d70e28f57e14a4 Len Brown 2016-03-13 1290 if (msr & (1 << 18))
0138d8f0755b5b Len Brown 2014-04-04 1291 return;
0138d8f0755b5b Len Brown 2014-04-04 1292 }
0138d8f0755b5b Len Brown 2014-04-04 1293
d70e28f57e14a4 Len Brown 2016-03-13 1294 skl_cstates[5].disabled = 1; /* C8-SKL */
d70e28f57e14a4 Len Brown 2016-03-13 1295 skl_cstates[6].disabled = 1; /* C9-SKL */
d70e28f57e14a4 Len Brown 2016-03-13 1296 }
d70e28f57e14a4 Len Brown 2016-03-13 1297 /*
d70e28f57e14a4 Len Brown 2016-03-13 1298 * intel_idle_state_table_update()
d70e28f57e14a4 Len Brown 2016-03-13 1299 *
d70e28f57e14a4 Len Brown 2016-03-13 1300 * Update the default state_table for this CPU-id
d70e28f57e14a4 Len Brown 2016-03-13 1301 */
d70e28f57e14a4 Len Brown 2016-03-13 1302
:::::: The code at line 1287 was first introduced by commit
:::::: d70e28f57e14a481977436695b0c9ba165472431 intel_idle: prevent SKL-H boot failure when C8+C9+C10 enabled
:::::: TO: Len Brown <len.brown@intel.com>
:::::: CC: Len Brown <len.brown@intel.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation
Hi Sean,
I love your patch! Yet something to improve:
[auto build test ERROR on tip/auto-latest]
[also build test ERROR on next-20191129]
[cannot apply to tip/x86/core kvm/linux-next v5.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Sean-Christopherson/x86-cpu-Clean-up-handling-of-VMX-features/20191128-094556
base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git e445033e58108a9891abfbc0dea90b066a75e4a9
config: x86_64-randconfig-s0-20191128 (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from arch/x86/include/asm/processor.h:22:0,
from arch/x86/include/asm/cpufeature.h:5,
from arch/x86/include/asm/thread_info.h:53,
from include/linux/thread_info.h:38,
from arch/x86/include/asm/preempt.h:7,
from include/linux/preempt.h:78,
from include/linux/percpu.h:6,
from include/linux/cpuidle.h:14,
from drivers/idle/intel_idle.c:45:
drivers/idle/intel_idle.c: In function 'sklh_idle_state_table_update':
>> drivers/idle/intel_idle.c:1287:10: error: 'MSR_IA32_FEATURE_CONTROL' undeclared (first use in this function); did you mean 'MSR_MISC_FEATURE_CONTROL'?
rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
^
arch/x86/include/asm/msr.h:279:28: note: in definition of macro 'rdmsrl'
((val) = native_read_msr((msr)))
^~~
drivers/idle/intel_idle.c:1287:10: note: each undeclared identifier is reported only once for each function it appears in
rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
^
arch/x86/include/asm/msr.h:279:28: note: in definition of macro 'rdmsrl'
((val) = native_read_msr((msr)))
^~~
vim +1287 drivers/idle/intel_idle.c
5dcef694860100 Len Brown 2016-04-06 1189
5dcef694860100 Len Brown 2016-04-06 1190 /*
5dcef694860100 Len Brown 2016-04-06 1191 * Translate IRTL (Interrupt Response Time Limit) MSR to usec
5dcef694860100 Len Brown 2016-04-06 1192 */
5dcef694860100 Len Brown 2016-04-06 1193
5dcef694860100 Len Brown 2016-04-06 1194 static unsigned int irtl_ns_units[] = {
5dcef694860100 Len Brown 2016-04-06 1195 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
5dcef694860100 Len Brown 2016-04-06 1196
5dcef694860100 Len Brown 2016-04-06 1197 static unsigned long long irtl_2_usec(unsigned long long irtl)
5dcef694860100 Len Brown 2016-04-06 1198 {
5dcef694860100 Len Brown 2016-04-06 1199 unsigned long long ns;
5dcef694860100 Len Brown 2016-04-06 1200
3451ab3ebf92b1 Jan Beulich 2016-06-27 1201 if (!irtl)
3451ab3ebf92b1 Jan Beulich 2016-06-27 1202 return 0;
3451ab3ebf92b1 Jan Beulich 2016-06-27 1203
bef450962597ff Jan Beulich 2016-06-27 1204 ns = irtl_ns_units[(irtl >> 10) & 0x7];
5dcef694860100 Len Brown 2016-04-06 1205
5dcef694860100 Len Brown 2016-04-06 1206 return div64_u64((irtl & 0x3FF) * ns, 1000);
5dcef694860100 Len Brown 2016-04-06 1207 }
5dcef694860100 Len Brown 2016-04-06 1208 /*
5dcef694860100 Len Brown 2016-04-06 1209 * bxt_idle_state_table_update(void)
5dcef694860100 Len Brown 2016-04-06 1210 *
5dcef694860100 Len Brown 2016-04-06 1211 * On BXT, we trust the IRTL to show the definitive maximum latency
5dcef694860100 Len Brown 2016-04-06 1212 * We use the same value for target_residency.
5dcef694860100 Len Brown 2016-04-06 1213 */
5dcef694860100 Len Brown 2016-04-06 1214 static void bxt_idle_state_table_update(void)
5dcef694860100 Len Brown 2016-04-06 1215 {
5dcef694860100 Len Brown 2016-04-06 1216 unsigned long long msr;
3451ab3ebf92b1 Jan Beulich 2016-06-27 1217 unsigned int usec;
5dcef694860100 Len Brown 2016-04-06 1218
5dcef694860100 Len Brown 2016-04-06 1219 rdmsrl(MSR_PKGC6_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1220 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1221 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1222 bxt_cstates[2].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1223 bxt_cstates[2].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1224 }
5dcef694860100 Len Brown 2016-04-06 1225
5dcef694860100 Len Brown 2016-04-06 1226 rdmsrl(MSR_PKGC7_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1227 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1228 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1229 bxt_cstates[3].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1230 bxt_cstates[3].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1231 }
5dcef694860100 Len Brown 2016-04-06 1232
5dcef694860100 Len Brown 2016-04-06 1233 rdmsrl(MSR_PKGC8_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1234 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1235 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1236 bxt_cstates[4].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1237 bxt_cstates[4].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1238 }
5dcef694860100 Len Brown 2016-04-06 1239
5dcef694860100 Len Brown 2016-04-06 1240 rdmsrl(MSR_PKGC9_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1241 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1242 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1243 bxt_cstates[5].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1244 bxt_cstates[5].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1245 }
5dcef694860100 Len Brown 2016-04-06 1246
5dcef694860100 Len Brown 2016-04-06 1247 rdmsrl(MSR_PKGC10_IRTL, msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1248 usec = irtl_2_usec(msr);
3451ab3ebf92b1 Jan Beulich 2016-06-27 1249 if (usec) {
5dcef694860100 Len Brown 2016-04-06 1250 bxt_cstates[6].exit_latency = usec;
5dcef694860100 Len Brown 2016-04-06 1251 bxt_cstates[6].target_residency = usec;
5dcef694860100 Len Brown 2016-04-06 1252 }
5dcef694860100 Len Brown 2016-04-06 1253
5dcef694860100 Len Brown 2016-04-06 1254 }
d70e28f57e14a4 Len Brown 2016-03-13 1255 /*
d70e28f57e14a4 Len Brown 2016-03-13 1256 * sklh_idle_state_table_update(void)
d70e28f57e14a4 Len Brown 2016-03-13 1257 *
d70e28f57e14a4 Len Brown 2016-03-13 1258 * On SKL-H (model 0x5e) disable C8 and C9 if:
d70e28f57e14a4 Len Brown 2016-03-13 1259 * C10 is enabled and SGX disabled
d70e28f57e14a4 Len Brown 2016-03-13 1260 */
d70e28f57e14a4 Len Brown 2016-03-13 1261 static void sklh_idle_state_table_update(void)
d70e28f57e14a4 Len Brown 2016-03-13 1262 {
d70e28f57e14a4 Len Brown 2016-03-13 1263 unsigned long long msr;
d70e28f57e14a4 Len Brown 2016-03-13 1264 unsigned int eax, ebx, ecx, edx;
d70e28f57e14a4 Len Brown 2016-03-13 1265
d70e28f57e14a4 Len Brown 2016-03-13 1266
d70e28f57e14a4 Len Brown 2016-03-13 1267 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
d70e28f57e14a4 Len Brown 2016-03-13 1268 if (max_cstate <= 7)
d70e28f57e14a4 Len Brown 2016-03-13 1269 return;
d70e28f57e14a4 Len Brown 2016-03-13 1270
d70e28f57e14a4 Len Brown 2016-03-13 1271 /* if PC10 not present in CPUID.MWAIT.EDX */
d70e28f57e14a4 Len Brown 2016-03-13 1272 if ((mwait_substates & (0xF << 28)) == 0)
d70e28f57e14a4 Len Brown 2016-03-13 1273 return;
d70e28f57e14a4 Len Brown 2016-03-13 1274
6cfb2374f83bc7 Len Brown 2017-01-07 1275 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
d70e28f57e14a4 Len Brown 2016-03-13 1276
d70e28f57e14a4 Len Brown 2016-03-13 1277 /* PC10 is not enabled in PKG C-state limit */
d70e28f57e14a4 Len Brown 2016-03-13 1278 if ((msr & 0xF) != 8)
d70e28f57e14a4 Len Brown 2016-03-13 1279 return;
d70e28f57e14a4 Len Brown 2016-03-13 1280
d70e28f57e14a4 Len Brown 2016-03-13 1281 ecx = 0;
d70e28f57e14a4 Len Brown 2016-03-13 1282 cpuid(7, &eax, &ebx, &ecx, &edx);
d70e28f57e14a4 Len Brown 2016-03-13 1283
d70e28f57e14a4 Len Brown 2016-03-13 1284 /* if SGX is present */
d70e28f57e14a4 Len Brown 2016-03-13 1285 if (ebx & (1 << 2)) {
d70e28f57e14a4 Len Brown 2016-03-13 1286
d70e28f57e14a4 Len Brown 2016-03-13 @1287 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
d70e28f57e14a4 Len Brown 2016-03-13 1288
d70e28f57e14a4 Len Brown 2016-03-13 1289 /* if SGX is enabled */
d70e28f57e14a4 Len Brown 2016-03-13 1290 if (msr & (1 << 18))
0138d8f0755b5b Len Brown 2014-04-04 1291 return;
0138d8f0755b5b Len Brown 2014-04-04 1292 }
0138d8f0755b5b Len Brown 2014-04-04 1293
d70e28f57e14a4 Len Brown 2016-03-13 1294 skl_cstates[5].disabled = 1; /* C8-SKL */
d70e28f57e14a4 Len Brown 2016-03-13 1295 skl_cstates[6].disabled = 1; /* C9-SKL */
d70e28f57e14a4 Len Brown 2016-03-13 1296 }
d70e28f57e14a4 Len Brown 2016-03-13 1297 /*
d70e28f57e14a4 Len Brown 2016-03-13 1298 * intel_idle_state_table_update()
d70e28f57e14a4 Len Brown 2016-03-13 1299 *
d70e28f57e14a4 Len Brown 2016-03-13 1300 * Update the default state_table for this CPU-id
d70e28f57e14a4 Len Brown 2016-03-13 1301 */
d70e28f57e14a4 Len Brown 2016-03-13 1302
:::::: The code at line 1287 was first introduced by commit
:::::: d70e28f57e14a481977436695b0c9ba165472431 intel_idle: prevent SKL-H boot failure when C8+C9+C10 enabled
:::::: TO: Len Brown <len.brown@intel.com>
:::::: CC: Len Brown <len.brown@intel.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation
On Sun, Dec 01, 2019 at 04:52:53AM +0800, kbuild test robot wrote: > Hi Sean, > > I love your patch! Yet something to improve: > > [auto build test ERROR on tip/auto-latest] > [also build test ERROR on next-20191129] > [cannot apply to tip/x86/core kvm/linux-next v5.4] > [if your patch is applied to the wrong git tree, please drop us a note to help > improve the system. BTW, we also suggest to use '--base' option to specify the > base tree in git format-patch, please see https://stackoverflow.com/a/37406982] > > url: https://github.com/0day-ci/linux/commits/Sean-Christopherson/x86-cpu-Clean-up-handling-of-VMX-features/20191128-094556 > base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git e445033e58108a9891abfbc0dea90b066a75e4a9 > config: x86_64-randconfig-s0-20191128 (attached as .config) > compiler: gcc-7 (Debian 7.4.0-14) 7.4.0 > reproduce: > # save the attached .config to linux build tree > make ARCH=x86_64 > > If you fix the issue, kindly add following tag > Reported-by: kbuild test robot <lkp@intel.com> > > All errors (new ones prefixed by >>): > > In file included from arch/x86/include/asm/processor.h:22:0, > from arch/x86/include/asm/cpufeature.h:5, > from arch/x86/include/asm/thread_info.h:53, > from include/linux/thread_info.h:38, > from arch/x86/include/asm/preempt.h:7, > from include/linux/preempt.h:78, > from include/linux/percpu.h:6, > from include/linux/cpuidle.h:14, > from drivers/idle/intel_idle.c:45: > drivers/idle/intel_idle.c: In function 'sklh_idle_state_table_update': > >> drivers/idle/intel_idle.c:1287:10: error: 'MSR_IA32_FEATURE_CONTROL' undeclared (first use in this function); did you mean 'MSR_MISC_FEATURE_CONTROL'? > rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); > ^ Argh, flat out missed this when doing search and replace. > arch/x86/include/asm/msr.h:279:28: note: in definition of macro 'rdmsrl' > ((val) = native_read_msr((msr))) > ^~~ > drivers/idle/intel_idle.c:1287:10: note: each undeclared identifier is reported only once for each function it appears in > rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); > ^ > arch/x86/include/asm/msr.h:279:28: note: in definition of macro 'rdmsrl' > ((val) = native_read_msr((msr))) > ^~~ > > vim +1287 drivers/idle/intel_idle.c
On Mon, Dec 02, 2019 at 11:06:33AM -0800, Sean Christopherson wrote:
> Argh, flat out missed this when doing search and replace.
There are more. What always works reliably for me is git grep:
$ git grep MSR_IA32_FEATURE_CONTROL
drivers/idle/intel_idle.c:1287: rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
tools/arch/x86/include/asm/msr-index.h:561:#define MSR_IA32_FEATURE_CONTROL 0x0000003a
tools/power/x86/turbostat/turbostat.c:4502: if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr))
tools/power/x86/turbostat/turbostat.c:4503: fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
tools/testing/selftests/kvm/include/x86_64/processor.h:771:#define MSR_IA32_FEATURE_CONTROL 0x0000003a
tools/testing/selftests/kvm/lib/x86_64/vmx.c:162: feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL);
tools/testing/selftests/kvm/lib/x86_64/vmx.c:164: wrmsr(MSR_IA32_FEATURE_CONTROL, feature_control | required);
those additional ones won't break the build but it is perhaps worth
unifying them all since we're at it, anyway.
Thx.
On Thu, Dec 12, 2019 at 10:25:09AM +0100, Borislav Petkov wrote: > On Mon, Dec 02, 2019 at 11:06:33AM -0800, Sean Christopherson wrote: > > Argh, flat out missed this when doing search and replace. > > There are more. What always works reliably for me is git grep: > > $ git grep MSR_IA32_FEATURE_CONTROL > drivers/idle/intel_idle.c:1287: rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); > tools/arch/x86/include/asm/msr-index.h:561:#define MSR_IA32_FEATURE_CONTROL 0x0000003a > tools/power/x86/turbostat/turbostat.c:4502: if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) > tools/power/x86/turbostat/turbostat.c:4503: fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", > tools/testing/selftests/kvm/include/x86_64/processor.h:771:#define MSR_IA32_FEATURE_CONTROL 0x0000003a > tools/testing/selftests/kvm/lib/x86_64/vmx.c:162: feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL); > tools/testing/selftests/kvm/lib/x86_64/vmx.c:164: wrmsr(MSR_IA32_FEATURE_CONTROL, feature_control | required); > > those additional ones won't break the build but it is perhaps worth > unifying them all since we're at it, anyway. I caught all the tools updates and addressed them in patch 03/19, "tools arch x86: Sync msr-index.h from kernel sources". Do you want those changes folded into the rename itself?
On Thu, Dec 12, 2019 at 09:48:01AM -0800, Sean Christopherson wrote: > I caught all the tools updates and addressed them in patch 03/19, "tools > arch x86: Sync msr-index.h from kernel sources". Do you want those changes > folded into the rename itself? Nah, it's ok as it is. Thx.
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 084e98da04a7..ebe1685e92dd 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -558,7 +558,14 @@ #define MSR_IA32_EBL_CR_POWERON 0x0000002a #define MSR_EBC_FREQUENCY_ID 0x0000002c #define MSR_SMI_COUNT 0x00000034 -#define MSR_IA32_FEATURE_CONTROL 0x0000003a + +/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ +#define MSR_IA32_FEAT_CTL 0x0000003a +#define FEAT_CTL_LOCKED BIT(0) +#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) +#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) +#define FEAT_CTL_LMCE_ENABLED BIT(20) + #define MSR_IA32_TSC_ADJUST 0x0000003b #define MSR_IA32_BNDCFGS 0x00000d90 @@ -566,11 +573,6 @@ #define MSR_IA32_XSS 0x00000da0 -#define FEATURE_CONTROL_LOCKED (1<<0) -#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) -#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) -#define FEATURE_CONTROL_LMCE (1<<20) - #define MSR_IA32_APICBASE 0x0000001b #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index e270d0770134..c238518b84a2 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -115,12 +115,12 @@ static bool lmce_supported(void) /* * BIOS should indicate support for LMCE by setting bit 20 in - * IA32_FEATURE_CONTROL without which touching MCG_EXT_CTL will - * generate a #GP fault. + * IA32_FEAT_CTL without which touching MCG_EXT_CTL will generate a #GP + * fault. */ - rdmsrl(MSR_IA32_FEATURE_CONTROL, tmp); - if ((tmp & (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE)) == - (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE)) + rdmsrl(MSR_IA32_FEAT_CTL, tmp); + if ((tmp & (FEAT_CTL_LOCKED | FEAT_CTL_LMCE_ENABLED)) == + (FEAT_CTL_LOCKED | FEAT_CTL_LMCE_ENABLED)) return true; return false; diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 4aea7d304beb..6879966b7648 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -4588,8 +4588,8 @@ static int handle_vmon(struct kvm_vcpu *vcpu) gpa_t vmptr; uint32_t revision; struct vcpu_vmx *vmx = to_vmx(vcpu); - const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED - | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; + const u64 VMXON_NEEDED_FEATURES = FEAT_CTL_LOCKED + | FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; /* * The Intel VMX Instruction Reference lists a bunch of bits that are diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 1b9ab4166397..ecf3ccf71bb2 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1839,11 +1839,11 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_MCG_EXT_CTL: if (!msr_info->host_initiated && !(vmx->msr_ia32_feature_control & - FEATURE_CONTROL_LMCE)) + FEAT_CTL_LMCE_ENABLED)) return 1; msr_info->data = vcpu->arch.mcg_ext_ctl; break; - case MSR_IA32_FEATURE_CONTROL: + case MSR_IA32_FEAT_CTL: msr_info->data = vmx->msr_ia32_feature_control; break; case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: @@ -2074,15 +2074,15 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_IA32_MCG_EXT_CTL: if ((!msr_info->host_initiated && !(to_vmx(vcpu)->msr_ia32_feature_control & - FEATURE_CONTROL_LMCE)) || + FEAT_CTL_LMCE_ENABLED)) || (data & ~MCG_EXT_CTL_LMCE_EN)) return 1; vcpu->arch.mcg_ext_ctl = data; break; - case MSR_IA32_FEATURE_CONTROL: + case MSR_IA32_FEAT_CTL: if (!vmx_feature_control_msr_valid(vcpu, data) || (to_vmx(vcpu)->msr_ia32_feature_control & - FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) + FEAT_CTL_LOCKED && !msr_info->host_initiated)) return 1; vmx->msr_ia32_feature_control = data; if (msr_info->host_initiated && data == 0) @@ -2206,22 +2206,22 @@ static __init int vmx_disabled_by_bios(void) { u64 msr; - rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); - if (msr & FEATURE_CONTROL_LOCKED) { + rdmsrl(MSR_IA32_FEAT_CTL, msr); + if (msr & FEAT_CTL_LOCKED) { /* launched w/ TXT and VMX disabled */ - if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) + if (!(msr & FEAT_CTL_VMX_ENABLED_INSIDE_SMX) && tboot_enabled()) return 1; /* launched w/o TXT and VMX only enabled w/ TXT */ - if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) - && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) + if (!(msr & FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX) + && (msr & FEAT_CTL_VMX_ENABLED_INSIDE_SMX) && !tboot_enabled()) { printk(KERN_WARNING "kvm: disable TXT in the BIOS or " "activate TXT before enabling KVM\n"); return 1; } /* launched w/o TXT and VMX disabled */ - if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) + if (!(msr & FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX) && !tboot_enabled()) return 1; } @@ -2269,16 +2269,16 @@ static int hardware_enable(void) */ crash_enable_local_vmclear(cpu); - rdmsrl(MSR_IA32_FEATURE_CONTROL, old); + rdmsrl(MSR_IA32_FEAT_CTL, old); - test_bits = FEATURE_CONTROL_LOCKED; - test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; + test_bits = FEAT_CTL_LOCKED; + test_bits |= FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; if (tboot_enabled()) - test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; + test_bits |= FEAT_CTL_VMX_ENABLED_INSIDE_SMX; if ((old & test_bits) != test_bits) { /* enable and lock */ - wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); + wrmsrl(MSR_IA32_FEAT_CTL, old | test_bits); } kvm_cpu_vmxon(phys_addr); if (enable_ept) @@ -6807,7 +6807,7 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) vmx->nested.posted_intr_nv = -1; vmx->nested.current_vmptr = -1ull; - vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED; + vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; /* * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR @@ -7107,12 +7107,12 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu) if (nested_vmx_allowed(vcpu)) to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= - FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX | - FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; + FEAT_CTL_VMX_ENABLED_INSIDE_SMX | + FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; else to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= - ~(FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX | - FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX); + ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | + FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); if (nested_vmx_allowed(vcpu)) { nested_vmx_cr_fixed1_bits_update(vcpu); @@ -7531,10 +7531,10 @@ static void vmx_setup_mce(struct kvm_vcpu *vcpu) { if (vcpu->arch.mcg_cap & MCG_LMCE_P) to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= - FEATURE_CONTROL_LMCE; + FEAT_CTL_LMCE_ENABLED; else to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= - ~FEATURE_CONTROL_LMCE; + ~FEAT_CTL_LMCE_ENABLED; } static int vmx_smi_allowed(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 7c1b978b2df4..b2c87f6be987 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -283,7 +283,7 @@ struct vcpu_vmx { /* * Only bits masked by msr_ia32_feature_control_valid_bits can be set in - * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included + * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included * in msr_ia32_feature_control_valid_bits. */ u64 msr_ia32_feature_control; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index cf917139de6b..740d3ee42455 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1142,7 +1142,7 @@ static const u32 msrs_to_save_all[] = { MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, #endif MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, - MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, + MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, MSR_IA32_SPEC_CTRL, MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
As pointed out by Boris, the defines for bits in IA32_FEATURE_CONTROL are quite a mouthful, especially the VMX bits which must differentiate between enabling VMX inside and outside SMX (TXT) operation. Rename the MSR and its bit defines to abbreviate FEATURE_CONTROL as FEAT_CTL to make them a little friendlier on the eyes. Arguably the MSR itself should keep the full IA32_FEATURE_CONTROL name to match Intel's SDM, but a future patch will add a dedicated Kconfig, file and functions for the MSR. Using the full name for those assets is rather unwieldy, so bite the bullet and use IA32_FEAT_CTL so that its nomenclature is consistent throughout the kernel. Opportunistically fix a few other annoyances with the defines: - Relocate the bit defines so that they immediately follow the MSR define, e.g. aren't mistaken as belonging to MISC_FEATURE_CONTROL. - Add whitespace around the block of feature control defines to make it clear they're all related. - Use BIT() instead of manually encoding the bit shift. - Use "VMX" instead of "VMXON" to match the SDM. - Append "_ENABLED" to the LMCE (Local Machine Check Exception) bit to be consistent with the kernel's verbiage used for all other feature control bits. Note, the SDM refers to the LMCE bit as LMCE_ON, likely to differentiate it from IA32_MCG_EXT_CTL.LMCE_EN. Ignore the (literal) one-off usage of _ON, the SDM is simply "wrong". Cc: Borislav Petkov <bp@alien8.de> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> --- arch/x86/include/asm/msr-index.h | 14 +++++----- arch/x86/kernel/cpu/mce/intel.c | 10 +++---- arch/x86/kvm/vmx/nested.c | 4 +-- arch/x86/kvm/vmx/vmx.c | 46 ++++++++++++++++---------------- arch/x86/kvm/vmx/vmx.h | 2 +- arch/x86/kvm/x86.c | 2 +- 6 files changed, 40 insertions(+), 38 deletions(-)