| Message ID | 20200908075716.30357-7-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | viresh kumar |
| Headers | show |
| Series | Add CPUFreq support for SM8250 SoC | expand |
On Tue, Sep 8, 2020 at 1:27 PM Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: > > SM8250 SoC uses EPSS block for carrying out the cpufreq duties. Hence, add > support for it in the driver with relevant of_match data. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Amit Kucheria <amitk@kernel.org> > --- > drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c > index de816bcafd33..c3c397cc3dc6 100644 > --- a/drivers/cpufreq/qcom-cpufreq-hw.c > +++ b/drivers/cpufreq/qcom-cpufreq-hw.c > @@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { > .lut_row_size = 32, > }; > > +static const struct qcom_cpufreq_soc_data sm8250_soc_data = { > + .reg_enable = 0x0, > + .reg_freq_lut = 0x100, > + .reg_volt_lut = 0x200, > + .reg_perf_state = 0x320, > + .lut_row_size = 4, > +}; > + > static const struct of_device_id qcom_cpufreq_hw_match[] = { > { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, > + { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data }, > {} > }; > MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); > -- > 2.17.1 >
On Tue 08 Sep 02:57 CDT 2020, Manivannan Sadhasivam wrote: > SM8250 SoC uses EPSS block for carrying out the cpufreq duties. Hence, add > support for it in the driver with relevant of_match data. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c > index de816bcafd33..c3c397cc3dc6 100644 > --- a/drivers/cpufreq/qcom-cpufreq-hw.c > +++ b/drivers/cpufreq/qcom-cpufreq-hw.c > @@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { > .lut_row_size = 32, > }; > > +static const struct qcom_cpufreq_soc_data sm8250_soc_data = { Could it be that this is the "epss_soc_data" (i.e. not sm8250 specific)? (We should still use/include the platform specific compatible though). Regards, Bjorn > + .reg_enable = 0x0, > + .reg_freq_lut = 0x100, > + .reg_volt_lut = 0x200, > + .reg_perf_state = 0x320, > + .lut_row_size = 4, > +}; > + > static const struct of_device_id qcom_cpufreq_hw_match[] = { > { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, > + { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data }, > {} > }; > MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); > -- > 2.17.1 >
On 0908, Bjorn Andersson wrote: > On Tue 08 Sep 02:57 CDT 2020, Manivannan Sadhasivam wrote: > > > SM8250 SoC uses EPSS block for carrying out the cpufreq duties. Hence, add > > support for it in the driver with relevant of_match data. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > > --- > > drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c > > index de816bcafd33..c3c397cc3dc6 100644 > > --- a/drivers/cpufreq/qcom-cpufreq-hw.c > > +++ b/drivers/cpufreq/qcom-cpufreq-hw.c > > @@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { > > .lut_row_size = 32, > > }; > > > > +static const struct qcom_cpufreq_soc_data sm8250_soc_data = { > > Could it be that this is the "epss_soc_data" (i.e. not sm8250 specific)? > (We should still use/include the platform specific compatible though). > Hmm, makes sense. Will change it. Thanks, Mani > Regards, > Bjorn > > > + .reg_enable = 0x0, > > + .reg_freq_lut = 0x100, > > + .reg_volt_lut = 0x200, > > + .reg_perf_state = 0x320, > > + .lut_row_size = 4, > > +}; > > + > > static const struct of_device_id qcom_cpufreq_hw_match[] = { > > { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, > > + { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data }, > > {} > > }; > > MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); > > -- > > 2.17.1 > >
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index de816bcafd33..c3c397cc3dc6 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { .lut_row_size = 32, }; +static const struct qcom_cpufreq_soc_data sm8250_soc_data = { + .reg_enable = 0x0, + .reg_freq_lut = 0x100, + .reg_volt_lut = 0x200, + .reg_perf_state = 0x320, + .lut_row_size = 4, +}; + static const struct of_device_id qcom_cpufreq_hw_match[] = { { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, + { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
SM8250 SoC uses EPSS block for carrying out the cpufreq duties. Hence, add support for it in the driver with relevant of_match data. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++ 1 file changed, 9 insertions(+)