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Wed, 21 Apr 2021 10:15:43 +0000 From: Dong Aisheng To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: dongas86@gmail.com, kernel@pengutronix.de, shawnguo@kernel.org, linux-imx@nxp.com, ulf.hansson@linaro.org, abel.vesa@nxp.com, Dong Aisheng Subject: [PATCH 2/3] firmware: imx: pd: add missing power domains Date: Wed, 21 Apr 2021 18:14:31 +0800 Message-Id: <20210421101432.2043310-2-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210421101432.2043310-1-aisheng.dong@nxp.com> References: <20210421101432.2043310-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: HK2PR02CA0213.apcprd02.prod.outlook.com (2603:1096:201:20::25) To AM6PR04MB4966.eurprd04.prod.outlook.com (2603:10a6:20b:2::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by HK2PR02CA0213.apcprd02.prod.outlook.com (2603:1096:201:20::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4042.16 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: UloRp7SJMfUofHTM0OXgoe9FvfFRf3rwvEsnOGo4bbJ7YsB+MnpVRs0F3DTVwWvjjRNOiHHJ8Ho5+4Xeno60IcdI3fXUR9Y5a6eKSGiDnYsenT/cngOrjUqR0z/wHL6mHJS4JTSa+FIx2rw7gVrJqg799idgVzPi3yY8s52oUuLPuHJWf/5EoheMmBUNpdSNOyUqGQ719H+R1JKmrorfmC0dLCOMTbx9TXiwJi/PWLCBvkc+PLariJE9hqXHivF7JVCMiUQKX2JhbbNbiTFmXJefiE5caZDxngfk+DT5UgBBI5MAVxVqR9JiAbv6HgkOTp/eA/EdfFDvCj5YTnSQtMR6CenaDg8CzQmMcknu0fB+vb3S61IiQKXb1Oxu53pNBdMfIrMJ+RzvdGiWlqh6WzxN7I/5Y6jVOtmwho24fKLaUqCpM9xd7J3nS+9usU8SsoW6JsiWFtlIisZwSyqqCghP6xALIBVwYijEjn7Y6aU+aKJalSTE175KXZcpE7tZ7YXPAxYvssR5Qb3RX058OY7JqGdji7HqF12rzHzXEtOzj4Db4QF4DVMECmTyDWLemTKXgjxQ5HbCZ2eqmJPI4QqTow9i5dDuCUBcCdeESoCjS/6UiqXUvev5wjf0iV0Tg4IY8+BNfYXuZkiTb1tnXUlgtalGqSYCPBsA7YJEusoJD6rcp0ZGQh0rte9PnYPzQmPkDdLcSrfukJF8Ht1oY8+E0p5O8Q7+mEisMOXr/Nl7qoCCv7PFgTBVMrftGIvf31LOrGUQL3YPFBaLe/Aq7rNHsvTqwm0EjxOuJhdEJBOPPlXqdq8HGY60DcmTokxlmv/mJUAPD0wYE9wCZuHkFy+KccOfZmcGN75joZqI3sU4wua9zFxDhTjQP0VSGCMk4UsTOOGDgKXWRkJLUVWs14IGHUJ6iQbMcn7H9P8K30YJ56L+rpPrZaWnr2m0v3G4U7dOuCgSD1dlRyUv63UBcitunmkv8HZ0e87LLpsGOFv/QTn6gqZB1EiqGvP06N6GlJ9joAWCyE7ckpWraNvC0KvV4HfU14797Wq+WyAsXZqOGmi+WWBEUKos71VDsBkDXSvVmHdN2Bm1lSo1jh2AiPT625K30EUBAYNiyM4XIvrUggMY/0XaGlUIg3zAtOw8yHSLq736GXE9Ym2aCx/pyukZ3Kk1/eRLpI97/l8ggylAKz2j50GkRf+aUlQTICTDETyc9X5kWBf5v1lOdMaH7tGjgHuy32C2Kjyy8/1oIeMn9Lo6PSgHmz0CYobqo4U1g5iFfOAO/HMppTMGRA5QxWiYs66PWcBQ0A4rf8dQdtAZRHxOwnyUApNyXiCR/EpR X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 55598049-6af3-451a-60c5-08d904ae6bf4 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4966.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2021 10:15:43.3283 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AWmDxGvfeX6DsaBAsnJB+f0fb70WYHFvXPWEvinqCx6llzU3DVsB0/1aJLl1DB4XIGU2qEOSqS3kNJxHwirgoA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB7687 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org A few power domains supported by SCFW are missing. Add them for driver users. Signed-off-by: Dong Aisheng --- drivers/firmware/imx/scu-pd.c | 69 +++++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index a7589cc5ac23..446a4f9f0ec9 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -120,12 +120,17 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 }, { "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 }, { "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 }, - { "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 }, + { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 }, { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 }, { "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, + { "dma2-ch", IMX_SC_R_DMA_2_CH5, 27, true, 5 }, + { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 }, { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 }, { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 }, { "esai0", IMX_SC_R_ESAI_0, 1, false, 0 }, + { "esai1", IMX_SC_R_ESAI_1, 1, false, 0 }, + { "mclk-out-0", IMX_SC_R_MCLK_OUT_0, 1, false, 0 }, + { "mclk-out-1", IMX_SC_R_MCLK_OUT_1, 1, false, 0 }, { "spdif0", IMX_SC_R_SPDIF_0, 1, false, 0 }, { "spdif1", IMX_SC_R_SPDIF_1, 1, false, 0 }, { "sai", IMX_SC_R_SAI_0, 3, true, 0 }, @@ -142,11 +147,13 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* DMA SS */ { "can", IMX_SC_R_CAN_0, 3, true, 0 }, { "ftm", IMX_SC_R_FTM_0, 2, true, 0 }, - { "lpi2c", IMX_SC_R_I2C_0, 4, true, 0 }, + { "lpi2c", IMX_SC_R_I2C_0, 5, true, 0 }, { "adc", IMX_SC_R_ADC_0, 2, true, 0 }, { "lcd", IMX_SC_R_LCD_0, 1, true, 0 }, + { "lcd-pll", IMX_SC_R_ELCDIF_PLL, 1, true, 0 }, { "lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, true, 0 }, - { "lpuart", IMX_SC_R_UART_0, 4, true, 0 }, + { "lpuart", IMX_SC_R_UART_0, 5, true, 0 }, + { "sim", IMX_SC_R_EMVSIM_0, 2, true, 0 }, { "lpspi", IMX_SC_R_SPI_0, 4, true, 0 }, { "irqstr_dsp", IMX_SC_R_IRQSTR_DSP, 1, false, 0 }, @@ -155,13 +162,21 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 }, + { "gpu1-pid", IMX_SC_R_GPU_1_PID0, 4, true, 0 }, /* HSIO SS */ + { "pcie-a", IMX_SC_R_PCIE_A, 1, false, 0 }, + { "serdes-0", IMX_SC_R_SERDES_0, 1, false, 0 }, { "pcie-b", IMX_SC_R_PCIE_B, 1, false, 0 }, { "serdes-1", IMX_SC_R_SERDES_1, 1, false, 0 }, + { "sata-0", IMX_SC_R_SATA_0, 1, false, 0 }, { "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, false, 0 }, /* MIPI SS */ @@ -175,13 +190,21 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* LVDS SS */ { "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 }, + { "lvds0-pwm", IMX_SC_R_LVDS_0_PWM_0, 1, false, 0 }, + { "lvds0-lpi2c", IMX_SC_R_LVDS_0_I2C_0, 2, true, 0 }, { "lvds1", IMX_SC_R_LVDS_1, 1, false, 0 }, + { "lvds1-pwm", IMX_SC_R_LVDS_1_PWM_0, 1, false, 0 }, + { "lvds1-lpi2c", IMX_SC_R_LVDS_1_I2C_0, 2, true, 0 }, /* DC SS */ { "dc0", IMX_SC_R_DC_0, 1, false, 0 }, { "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 }, { "dc0-video", IMX_SC_R_DC_0_VIDEO0, 2, true, 0 }, + { "dc1", IMX_SC_R_DC_1, 1, false, 0 }, + { "dc1-pll", IMX_SC_R_DC_1_PLL_0, 2, true, 0 }, + { "dc1-video", IMX_SC_R_DC_1_VIDEO0, 2, true, 0 }, + /* CM40 SS */ { "cm40-i2c", IMX_SC_R_M4_0_I2C, 1, false, 0 }, { "cm40-intmux", IMX_SC_R_M4_0_INTMUX, 1, false, 0 }, @@ -196,11 +219,51 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "cm41-mu-a1", IMX_SC_R_M4_1_MU_1A, 1, false, 0}, { "cm41-lpuart", IMX_SC_R_M4_1_UART, 1, false, 0}, + /* CM41 SS */ + { "cm41_i2c", IMX_SC_R_M4_1_I2C, 1, false, 0 }, + { "cm41_intmux", IMX_SC_R_M4_1_INTMUX, 1, false, 0 }, + + /* DB SS */ + { "perf", IMX_SC_R_PERF, 1, false, 0}, + /* IMAGE SS */ { "img-jpegdec-mp", IMX_SC_R_MJPEG_DEC_MP, 1, false, 0 }, { "img-jpegdec-s", IMX_SC_R_MJPEG_DEC_S0, 4, true, 0 }, { "img-jpegenc-mp", IMX_SC_R_MJPEG_ENC_MP, 1, false, 0 }, { "img-jpegenc-s", IMX_SC_R_MJPEG_ENC_S0, 4, true, 0 }, + { "img-pdma", IMX_SC_R_ISI_CH0, 8, true, 0 }, + { "img-csi0", IMX_SC_R_CSI_0, 1, false, 0 }, + { "img-csi0-i2c0", IMX_SC_R_CSI_0_I2C_0, 1, false, 0 }, + { "img-csi0-pwm0", IMX_SC_R_CSI_0_PWM_0, 1, false, 0 }, + { "img-csi1", IMX_SC_R_CSI_1, 1, false, 0 }, + { "img-csi1-i2c0", IMX_SC_R_CSI_1_I2C_0, 1, false, 0 }, + { "img-csi1-pwm0", IMX_SC_R_CSI_1_PWM_0, 1, false, 0 }, + { "img-parallel", IMX_SC_R_PI_0, 1, false, 0 }, + { "img-parallel-i2c0", IMX_SC_R_PI_0_I2C_0, 1, false, 0 }, + { "img-parallel-pwm", IMX_SC_R_PI_0_PWM_0, 2, true, 0 }, + { "img-parallel-pll", IMX_SC_R_PI_0_PLL, 1, false, 0 }, + + /* SECO SS */ + { "seco_mu", IMX_SC_R_SECO_MU_2, 3, true, 2}, + + /* HDMI TX SS */ + { "hdmi-tx", IMX_SC_R_HDMI, 1, false, 0}, + { "hdmi-tx-i2s", IMX_SC_R_HDMI_I2S, 1, false, 0}, + { "hdmi-tx-i2c0", IMX_SC_R_HDMI_I2C_0, 1, false, 0}, + { "hdmi-tx-pll0", IMX_SC_R_HDMI_PLL_0, 1, false, 0}, + { "hdmi-tx-pll1", IMX_SC_R_HDMI_PLL_1, 1, false, 0}, + + /* HDMI RX SS */ + { "hdmi-rx", IMX_SC_R_HDMI_RX, 1, false, 0}, + { "hdmi-rx-pwm0", IMX_SC_R_HDMI_RX_PWM_0, 1, false, 0}, + { "hdmi-rx-i2c0", IMX_SC_R_HDMI_RX_I2C_0, 1, false, 0}, + { "hdmi-rx-bypass", IMX_SC_R_HDMI_RX_BYPASS, 1, false, 0}, + + /* SECURITY SS */ + { "sec-jr", IMX_SC_R_CAAM_JR2, 2, true, 2}, + + /* BOARD SS */ + { "board", IMX_SC_R_BOARD_R0, 8, true, 0}, }; static const struct imx_sc_pd_soc imx8qxp_scu_pd = {