From patchwork Fri Apr 8 08:00:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5312BC433EF for ; Fri, 8 Apr 2022 07:58:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230150AbiDHIAh (ORCPT ); Fri, 8 Apr 2022 04:00:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230110AbiDHIAb (ORCPT ); Fri, 8 Apr 2022 04:00:31 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9582816E205; Fri, 8 Apr 2022 00:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649404708; x=1680940708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o5AzebHFW+wKVCswo1mni6dGq0V0+Rg/eIh7HzLox4c=; b=SQHi70LsC1wyDIOvmBwcZNx2V7b8tiRa34GzM2N+MIja4bXcynZFDQfi GlmlcHnwuLrNpzhl07fi7MNpFgRn7zFYWvWpZ27+nyfhgJQnxKur7JEGO MZ8qYHMzPNVwbMargUQN+DzPj8ZjQv9Qg9CRNqHJ79MZaZlwS1/XSshO9 GeLoMG8dT0kyz1GNkcYWvMYaA7XJmS0XYG6bzablMuEhJxeQ20kkjRyFJ rdfm5CiCj2aOg3PDWpXXToS1fCV6KbWrUtGtAzqcizVYsNl4k4Ig8lf5H DzCjOgLl3yw8tAcaCHozRMX+OxnlZffqvH2yMqZm7nM2Jwh19zTiwzin1 g==; X-IronPort-AV: E=Sophos;i="5.90,244,1643698800"; d="scan'208";a="159403651" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 00:58:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:27 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:24 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea , Rob Herring Subject: [PATCH v3 03/10] dt-bindings: reset: atmel,at91sam9260-reset: add sama7g5 bindings Date: Fri, 8 Apr 2022 11:00:24 +0300 Message-ID: <20220408080031.2527232-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add documentation for SAMA7G5 reset controller. Compared with previous versions of reset controllers this one contains support for resetting in SoC devices (e.g. USB PHYs). Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring --- .../reset/atmel,at91sam9260-reset.yaml | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 34c40b875e20..98465d26949e 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -10,7 +10,8 @@ maintainers: - Claudiu Beznea description: | - The system reset controller can be used to reset the CPU. + The system reset controller can be used to reset the CPU. In case of + SAMA7G5 it can also reset some devices (e.g. USB PHYs). properties: compatible: @@ -21,21 +22,39 @@ properties: - atmel,at91sam9g45-rstc - atmel,sama5d3-rstc - microchip,sam9x60-rstc + - microchip,sama7g5-rstc - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc reg: - maxItems: 1 + minItems: 1 + items: + - description: base registers for system reset control + - description: registers for device specific reset control clocks: maxItems: 1 + "#reset-cells": + const: 1 + required: - compatible - reg - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sama7g5-rstc + then: + required: + - "#reset-cells" + additionalProperties: false examples: