From patchwork Mon May 16 02:15:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: qianfan X-Patchwork-Id: 12850205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29A68C433F5 for ; Mon, 16 May 2022 02:16:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238716AbiEPCQR (ORCPT ); Sun, 15 May 2022 22:16:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230396AbiEPCQO (ORCPT ); Sun, 15 May 2022 22:16:14 -0400 Received: from m12-12.163.com (m12-12.163.com [220.181.12.12]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2F17628993; Sun, 15 May 2022 19:16:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=yJNGb iMjW6rW2oUi41YYZWCz/tahmAPLKD7bIx55rSo=; b=JBoxfjGqpyvnDvM5EQVYP 5gdwDs/cunPbRhhwsaiPyxcnHUmAVd+HdfOrTKPpNxEuO47jMUT0Q/bHm3KE8gOI 0v8nKfo1IFgAzOOJkE8zkctwCZfHQENuYCQPSrE8aAC1bj4xFpoiLaoqlzMuM7Xt v9UOHVQ/uOElfsqUjr9fo8= Received: from DESKTOP-B1R4FVG.localdomain (unknown [218.201.129.19]) by smtp8 (Coremail) with SMTP id DMCowACHYyG1s4Fi8FLcCg--.16808S4; Mon, 16 May 2022 10:15:20 +0800 (CST) From: qianfanguijin@163.com To: linux-sunxi@lists.linux.dev Cc: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , "Rafael J . Wysocki" , Viresh Kumar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, qianfan Zhao Subject: [PATCH v4 2/2] ARM: dts: sun8i-r40: add opp table for cpu Date: Mon, 16 May 2022 10:15:16 +0800 Message-Id: <20220516021516.23216-3-qianfanguijin@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220516021516.23216-1-qianfanguijin@163.com> References: <20220516021516.23216-1-qianfanguijin@163.com> MIME-Version: 1.0 X-CM-TRANSID: DMCowACHYyG1s4Fi8FLcCg--.16808S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7uw47XryfXry3Xw4xJryfXrb_yoW8uFyfpr 4ak3yFkF48Wr12qw1aqw10qFyruayvvF4UJrnrC3y8t34YqryDtryxtry3K3yDXr47X3yS qrsIqry2kw1DA3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07UbjjDUUUUU= X-Originating-IP: [218.201.129.19] X-CM-SenderInfo: htld0w5dqj3xxmlqqiywtou0bp/xtbB2AgD7WBHKdE-OgAAsk Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: qianfan Zhao OPP table value is get from allwinner lichee linux-3.10 kernel driver Signed-off-by: qianfan Zhao --- arch/arm/boot/dts/sun8i-r40.dtsi | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 291f4784e86c..8949153eb0eb 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -54,6 +54,36 @@ / { #size-cells = <1>; interrupt-parent = <&gic>; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1000000 1000000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1100000 1100000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1160000 1160000 1300000>; + clock-latency-ns = <2000000>; + }; + + /* The opp table of the cpu frequency that exceeds 1G + * is not defined here. They require higher operating + * current, which may exceed the 500mA limited if the + * system is powered by USB. You can add them to the + * board's DTS is you make sure. + */ + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -84,24 +114,36 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; }; };