| Message ID | 20221111032515.3460-4-quic_bjorande@quicinc.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | interconnect: osm-l3: SC8280XP L3 and DDR scaling | expand |
On 11/11/22 08:55, Bjorn Andersson wrote: > The EPSS instance in e.g. SM8350 and SC8280XP has per-core L3 voting > enabled. In this configuration, the "shared" vote is done using the > REG_L3_VOTE register instead of PERF_STATE. > > Rename epss_l3 to clarify that it's affecting the PERF_STATE register > and add a new L3_VOTE description. Given platform lineage it's assumed > that the L3_VOTE-based case will be the predominant one, so use this for > a new generic qcom,epss-l3 compatible. > > While adding the EPSS generic, also add qcom,osm-l3. > > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> > --- > > Changes since v1: > - None > > drivers/interconnect/qcom/osm-l3.c | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c > index 7d6844253241..469be732a00b 100644 > --- a/drivers/interconnect/qcom/osm-l3.c > +++ b/drivers/interconnect/qcom/osm-l3.c > @@ -34,6 +34,7 @@ > > /* EPSS Register offsets */ > #define EPSS_LUT_ROW_SIZE 4 > +#define EPSS_REG_L3_VOTE 0x90 > #define EPSS_REG_FREQ_LUT 0x100 > #define EPSS_REG_PERF_STATE 0x320 > > @@ -112,7 +113,7 @@ static const struct qcom_osm_l3_desc osm_l3 = { > .reg_perf_state = OSM_REG_PERF_STATE, > }; > > -static const struct qcom_osm_l3_desc epss_l3 = { > +static const struct qcom_osm_l3_desc epss_l3_perf_state = { > .nodes = epss_l3_nodes, > .num_nodes = ARRAY_SIZE(epss_l3_nodes), > .lut_row_size = EPSS_LUT_ROW_SIZE, > @@ -120,6 +121,14 @@ static const struct qcom_osm_l3_desc epss_l3 = { > .reg_perf_state = EPSS_REG_PERF_STATE, > }; > > +static const struct qcom_osm_l3_desc epss_l3_l3_vote = { > + .nodes = epss_l3_nodes, > + .num_nodes = ARRAY_SIZE(epss_l3_nodes), > + .lut_row_size = EPSS_LUT_ROW_SIZE, > + .reg_freq_lut = EPSS_REG_FREQ_LUT, > + .reg_perf_state = EPSS_REG_L3_VOTE, > +}; > + > static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst) > { > struct qcom_osm_l3_icc_provider *qp; > @@ -285,12 +294,14 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) > } > > static const struct of_device_id osm_l3_of_match[] = { > + { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote }, > + { .compatible = "qcom,osm-l3", .data = &osm_l3 }, > { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, > - { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 }, > + { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state }, > { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 }, > { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 }, > { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 }, > - { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 }, > + { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state }, > { } > }; > MODULE_DEVICE_TABLE(of, osm_l3_of_match);
diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 7d6844253241..469be732a00b 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -34,6 +34,7 @@ /* EPSS Register offsets */ #define EPSS_LUT_ROW_SIZE 4 +#define EPSS_REG_L3_VOTE 0x90 #define EPSS_REG_FREQ_LUT 0x100 #define EPSS_REG_PERF_STATE 0x320 @@ -112,7 +113,7 @@ static const struct qcom_osm_l3_desc osm_l3 = { .reg_perf_state = OSM_REG_PERF_STATE, }; -static const struct qcom_osm_l3_desc epss_l3 = { +static const struct qcom_osm_l3_desc epss_l3_perf_state = { .nodes = epss_l3_nodes, .num_nodes = ARRAY_SIZE(epss_l3_nodes), .lut_row_size = EPSS_LUT_ROW_SIZE, @@ -120,6 +121,14 @@ static const struct qcom_osm_l3_desc epss_l3 = { .reg_perf_state = EPSS_REG_PERF_STATE, }; +static const struct qcom_osm_l3_desc epss_l3_l3_vote = { + .nodes = epss_l3_nodes, + .num_nodes = ARRAY_SIZE(epss_l3_nodes), + .lut_row_size = EPSS_LUT_ROW_SIZE, + .reg_freq_lut = EPSS_REG_FREQ_LUT, + .reg_perf_state = EPSS_REG_L3_VOTE, +}; + static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst) { struct qcom_osm_l3_icc_provider *qp; @@ -285,12 +294,14 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) } static const struct of_device_id osm_l3_of_match[] = { + { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote }, + { .compatible = "qcom,osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, - { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 }, + { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state }, { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 }, - { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 }, + { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state }, { } }; MODULE_DEVICE_TABLE(of, osm_l3_of_match);