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[83.9.32.53]) by smtp.gmail.com with ESMTPSA id q11-20020a056512210b00b004cc9042c9cfsm928888lfr.158.2023.01.11.12.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 12:51:31 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] cpufreq: qcom-hw: Ensure only freq-domain regs are counted in num_domains Date: Wed, 11 Jan 2023 21:51:25 +0100 Message-Id: <20230111205125.1860858-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111205125.1860858-1-konrad.dybcio@linaro.org> References: <20230111205125.1860858-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In preparation for CPRh-aware OSM programming, change the probe function so that we determine the number of frequency domains by counting the number of reg-names entries that begin with "freq-domain", as the aforementioned changes require introduction of non-freq-domain register spaces. Fixes: 1a6a8b0080b0 ("cpufreq: qcom-hw: Fix reading "reg" with address/size-cells != 2") Fixes: 054a3ef683a1 ("cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe") Signed-off-by: Konrad Dybcio --- drivers/cpufreq/qcom-cpufreq-hw.c | 34 ++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 9505a812d6a1..89d5ed267399 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -651,8 +651,9 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *soc_node; struct device *cpu_dev; + const char *reg_name; struct clk *clk; - int ret, i, num_domains, reg_sz; + int ret, i, num_reg_names, num_domains = 0; clk = clk_get(dev, "xo"); if (IS_ERR(clk)) @@ -684,19 +685,32 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) if (!soc_node) return -EINVAL; - ret = of_property_read_u32(soc_node, "#address-cells", ®_sz); - if (ret) + num_reg_names = of_property_count_strings(dev->of_node, "reg-names"); + if (num_reg_names <= 0) { + ret = num_reg_names ? num_reg_names : -ENODATA; goto of_exit; + } - ret = of_property_read_u32(soc_node, "#size-cells", &i); - if (ret) - goto of_exit; + for (i = 0; i < num_reg_names; i++) { + ret = of_property_read_string_index(dev->of_node, "reg-names", i, ®_name); + if (ret < 0) + goto of_exit; - reg_sz += i; + /* + * Check if the i-th reg is a freq-domain base, no need to add 1 + * more byte for idx, as sizeof counts \0 whereas strlen does not. + */ + if (strlen(reg_name) == sizeof("freq-domain")) { + /* Check if this reg-name begins with "freq-domain" */ + if (!strncmp(reg_name, "freq-domain", sizeof("freq-domain") - 1)) + num_domains++; + } + } - num_domains = of_property_count_elems_of_size(dev->of_node, "reg", sizeof(u32) * reg_sz); - if (num_domains <= 0) - return num_domains; + if (num_domains <= 0) { + ret = -EINVAL; + goto of_exit; + } qcom_cpufreq.data = devm_kzalloc(dev, sizeof(struct qcom_cpufreq_data) * num_domains, GFP_KERNEL);