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Mon, 22 May 2023 06:34:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT041.mail.protection.outlook.com (10.13.172.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.28 via Frontend Transport; Mon, 22 May 2023 06:34:22 +0000 Received: from beas.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 22 May 2023 01:34:19 -0500 From: Wyes Karny To: , , CC: , , , , , Wyes Karny Subject: [PATCH 1/2] cpufreq/amd-pstate: Write CPPC enable bit for each core Date: Mon, 22 May 2023 06:33:24 +0000 Message-ID: <20230522063325.80193-2-wyes.karny@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230522063325.80193-1-wyes.karny@amd.com> References: <20230522063325.80193-1-wyes.karny@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT041:EE_|DS0PR12MB8788:EE_ X-MS-Office365-Filtering-Correlation-Id: 0eab8898-41dd-40b1-a8ef-08db5a8e94b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2023 06:34:22.9130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0eab8898-41dd-40b1-a8ef-08db5a8e94b6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8788 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org ACPI specification [1] says: "CPPC Enable Register: If supported by the platform, OSPM writes a one to this register to enable CPPC on this processor." Make amd_pstate align with the specification. To do so, move amd_pstate_enable function to per-policy/per-core callbacks. Also remove per-cpu loop from cppc_enable, because it's called from per-policy/per-core callbacks and it was causing duplicate MSR writes. This will improve driver-load, suspend-resume and offline-online on shared memory system. [1]: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/08_Processor_Configuration_and_Control/declaring-processors.html#cppc-enable-register Fixes: e059c184da47 ("cpufreq: amd-pstate: Introduce the support for the processors with shared memory solution") Signed-off-by: Wyes Karny --- drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5a3d4aa0f45a..8c72f95ac315 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -226,29 +226,27 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, return ret; } -static inline int pstate_enable(bool enable) +static inline int pstate_enable(int cpu, bool enable) { - return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable); + return wrmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_ENABLE, enable); } -static int cppc_enable(bool enable) +static int cppc_enable(int cpu, bool enable) { - int cpu, ret = 0; + int ret = 0; struct cppc_perf_ctrls perf_ctrls; - for_each_present_cpu(cpu) { - ret = cppc_set_enable(cpu, enable); + ret = cppc_set_enable(cpu, enable); + if (ret) + return ret; + + /* Enable autonomous mode for EPP */ + if (cppc_state == AMD_PSTATE_ACTIVE) { + /* Set desired perf as zero to allow EPP firmware control */ + perf_ctrls.desired_perf = 0; + ret = cppc_set_perf(cpu, &perf_ctrls); if (ret) return ret; - - /* Enable autonomous mode for EPP */ - if (cppc_state == AMD_PSTATE_ACTIVE) { - /* Set desired perf as zero to allow EPP firmware control */ - perf_ctrls.desired_perf = 0; - ret = cppc_set_perf(cpu, &perf_ctrls); - if (ret) - return ret; - } } return ret; @@ -256,9 +254,9 @@ static int cppc_enable(bool enable) DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable); -static inline int amd_pstate_enable(bool enable) +static inline int amd_pstate_enable(int cpu, bool enable) { - return static_call(amd_pstate_enable)(enable); + return static_call(amd_pstate_enable)(cpu, enable); } static int pstate_init_perf(struct amd_cpudata *cpudata) @@ -643,6 +641,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; + ret = amd_pstate_enable(policy->cpu, true); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -724,7 +724,7 @@ static int amd_pstate_cpu_resume(struct cpufreq_policy *policy) { int ret; - ret = amd_pstate_enable(true); + ret = amd_pstate_enable(policy->cpu, true); if (ret) pr_err("failed to enable amd-pstate during resume, return %d\n", ret); @@ -735,7 +735,7 @@ static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy) { int ret; - ret = amd_pstate_enable(false); + ret = amd_pstate_enable(policy->cpu, false); if (ret) pr_err("failed to disable amd-pstate during suspend, return %d\n", ret); @@ -841,7 +841,6 @@ static ssize_t show_energy_performance_preference( static void amd_pstate_driver_cleanup(void) { - amd_pstate_enable(false); cppc_state = AMD_PSTATE_DISABLE; current_pstate_driver = NULL; } @@ -1039,6 +1038,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; cpudata->epp_policy = 0; + ret = amd_pstate_enable(policy->cpu, true); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1180,13 +1181,13 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) return 0; } -static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) +static void amd_pstate_epp_reenable(int cpu, struct amd_cpudata *cpudata) { struct cppc_perf_ctrls perf_ctrls; u64 value, max_perf; int ret; - ret = amd_pstate_enable(true); + ret = amd_pstate_enable(cpu, true); if (ret) pr_err("failed to enable amd pstate during resume, return %d\n", ret); @@ -1209,7 +1210,7 @@ static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) pr_debug("AMD CPU Core %d going online\n", cpudata->cpu); if (cppc_state == AMD_PSTATE_ACTIVE) { - amd_pstate_epp_reenable(cpudata); + amd_pstate_epp_reenable(policy->cpu, cpudata); cpudata->suspended = false; } @@ -1280,7 +1281,7 @@ static int amd_pstate_epp_suspend(struct cpufreq_policy *policy) cpudata->suspended = true; /* disable CPPC in lowlevel firmware */ - ret = amd_pstate_enable(false); + ret = amd_pstate_enable(policy->cpu, false); if (ret) pr_err("failed to suspend, return %d\n", ret); @@ -1295,7 +1296,7 @@ static int amd_pstate_epp_resume(struct cpufreq_policy *policy) mutex_lock(&amd_pstate_limits_lock); /* enable amd pstate from suspend state*/ - amd_pstate_epp_reenable(cpudata); + amd_pstate_epp_reenable(policy->cpu, cpudata); mutex_unlock(&amd_pstate_limits_lock); @@ -1370,8 +1371,6 @@ static int __init amd_pstate_init(void) static_call_update(amd_pstate_update_perf, cppc_update_perf); } - /* enable amd pstate feature */ - ret = amd_pstate_enable(true); if (ret) { pr_err("failed to enable with return %d\n", ret); return ret;