| Message ID | 20230529164605.3552619-2-bero@baylibre.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add LVTS support for mt8192 | expand |
On 29/05/2023 18:46, Bernhard Rosenkränzer wrote: > From: Balsam CHIHI <bchihi@baylibre.com> > > Add LVTS thermal controller definition for MT8192. > > Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h > index 8fa5a46675c46..5e9eb62174268 100644 > --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h > +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h > @@ -26,4 +26,23 @@ > #define MT8195_AP_CAM0 15 > #define MT8195_AP_CAM1 16 > > +#define MT8192_MCU_BIG_CPU0 0 > +#define MT8192_MCU_BIG_CPU1 1 > +#define MT8192_MCU_BIG_CPU2 2 > +#define MT8192_MCU_BIG_CPU3 3 > +#define MT8192_MCU_LITTLE_CPU0 4 > +#define MT8192_MCU_LITTLE_CPU1 5 > +#define MT8192_MCU_LITTLE_CPU2 6 > +#define MT8192_MCU_LITTLE_CPU3 7 > + > +#define MT8192_AP_VPU0 8 > +#define MT8192_AP_VPU1 9 > +#define MT8192_AP_GPU0 10 > +#define MT8192_AP_GPU1 11 > +#define MT8192_AP_INFRA 12 > +#define MT8192_AP_CAM 13 > +#define MT8192_AP_MD0 14 > +#define MT8192_AP_MD1 15 > +#define MT8192_AP_MD2 16 > + > #endif /* __MEDIATEK_LVTS_DT_H */
diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h index 8fa5a46675c46..5e9eb62174268 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -26,4 +26,23 @@ #define MT8195_AP_CAM0 15 #define MT8195_AP_CAM1 16 +#define MT8192_MCU_BIG_CPU0 0 +#define MT8192_MCU_BIG_CPU1 1 +#define MT8192_MCU_BIG_CPU2 2 +#define MT8192_MCU_BIG_CPU3 3 +#define MT8192_MCU_LITTLE_CPU0 4 +#define MT8192_MCU_LITTLE_CPU1 5 +#define MT8192_MCU_LITTLE_CPU2 6 +#define MT8192_MCU_LITTLE_CPU3 7 + +#define MT8192_AP_VPU0 8 +#define MT8192_AP_VPU1 9 +#define MT8192_AP_GPU0 10 +#define MT8192_AP_GPU1 11 +#define MT8192_AP_INFRA 12 +#define MT8192_AP_CAM 13 +#define MT8192_AP_MD0 14 +#define MT8192_AP_MD1 15 +#define MT8192_AP_MD2 16 + #endif /* __MEDIATEK_LVTS_DT_H */