| Message ID | 20230827115033.935089-16-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | ARM: qcom: apq8064: support CPU frequency scaling | expand |
On 27.08.2023 13:50, Dmitry Baryshkov wrote: > Add device node for the clock controller for the CPU cores and L2 > clocks. It will be further used by the L2 and by the CPUfreq nodes. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 26 ++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > index ba7d5ef8de17..a05e64bff07f 100644 > --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > @@ -213,6 +213,32 @@ sleep_clk: sleep_clk { > }; > }; > > + kraitcc: clock-controller { > + compatible = "qcom,krait-cc-v1"; > + clocks = <&gcc PLL9>, > + <&gcc PLL10>, > + <&gcc PLL16>, > + <&gcc PLL17>, > + <&gcc PLL12>, > + <&acc0>, > + <&acc1>, > + <&acc2>, > + <&acc3>, > + <&l2cc>; > + clock-names = "hfpll0", > + "hfpll1", > + "hfpll2", > + "hfpll3", > + "hfpll_l2", > + "acpu0_aux", > + "acpu1_aux", > + "acpu2_aux", > + "acpu3_aux", > + "acpu_l2_aux"; > + #clock-cells = <1>; > + #interconnect-cells = <1>; Doesn't only the L2 device register with icc? Konrad
On Mon, 28 Aug 2023 at 13:54, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > On 27.08.2023 13:50, Dmitry Baryshkov wrote: > > Add device node for the clock controller for the CPU cores and L2 > > clocks. It will be further used by the L2 and by the CPUfreq nodes. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 26 ++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > index ba7d5ef8de17..a05e64bff07f 100644 > > --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > @@ -213,6 +213,32 @@ sleep_clk: sleep_clk { > > }; > > }; > > > > + kraitcc: clock-controller { > > + compatible = "qcom,krait-cc-v1"; > > + clocks = <&gcc PLL9>, > > + <&gcc PLL10>, > > + <&gcc PLL16>, > > + <&gcc PLL17>, > > + <&gcc PLL12>, > > + <&acc0>, > > + <&acc1>, > > + <&acc2>, > > + <&acc3>, > > + <&l2cc>; > > + clock-names = "hfpll0", > > + "hfpll1", > > + "hfpll2", > > + "hfpll3", > > + "hfpll_l2", > > + "acpu0_aux", > > + "acpu1_aux", > > + "acpu2_aux", > > + "acpu3_aux", > > + "acpu_l2_aux"; > > + #clock-cells = <1>; > > + #interconnect-cells = <1>; > Doesn't only the L2 device register with icc? True. I'll drop this -- With best wishes Dmitry
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index ba7d5ef8de17..a05e64bff07f 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -213,6 +213,32 @@ sleep_clk: sleep_clk { }; }; + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, + <&gcc PLL10>, + <&gcc PLL16>, + <&gcc PLL17>, + <&gcc PLL12>, + <&acc0>, + <&acc1>, + <&acc2>, + <&acc3>, + <&l2cc>; + clock-names = "hfpll0", + "hfpll1", + "hfpll2", + "hfpll3", + "hfpll_l2", + "acpu0_aux", + "acpu1_aux", + "acpu2_aux", + "acpu3_aux", + "acpu_l2_aux"; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; + sfpb_mutex: hwmutex { compatible = "qcom,sfpb-mutex"; syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
Add device node for the clock controller for the CPU cores and L2 clocks. It will be further used by the L2 and by the CPUfreq nodes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+)