| Message ID | 20230829064340.1136448-4-li.meng@amd.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | AMD Pstate Preferred Core | expand |
On Tue, Aug 29, 2023 at 02:43:36PM +0800, Meng, Li (Jassmine) wrote: > AMD Pstate driver utilizes the functions and data structures > provided by the ITMT architecture to enable the scheduler to > favor scheduling on cores which can be get a higher frequency > with lower voltage. We call it AMD Pstate Preferrred Core. > > Here sched_set_itmt_core_prio() is called to set priorities and > sched_set_itmt_support() is called to enable ITMT feature. > AMD Pstate driver uses the highest performance value to indicate > the priority of CPU. The higher value has a higher priority. > > The initial core rankings are set up by AMD Pstate when the > system boots. > > Add device attribute for preferred core states. > > Add one new early parameter `enable` to allow user to > enable the preferred core if the processor and power > firmware can support preferred core feature. > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> > Co-developed-by: Perry Yuan <Perry.Yuan@amd.com> > Signed-off-by: Meng Li <li.meng@amd.com> > Co-developed-by: Meng Li <li.meng@amd.com> > Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> > --- > drivers/cpufreq/amd-pstate.c | 120 ++++++++++++++++++++++++++++++----- > 1 file changed, 104 insertions(+), 16 deletions(-) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 9a1e194d5cf8..d02305675f66 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -37,6 +37,7 @@ > #include <linux/uaccess.h> > #include <linux/static_call.h> > #include <linux/amd-pstate.h> > +#include <linux/topology.h> > > #include <acpi/processor.h> > #include <acpi/cppc_acpi.h> > @@ -49,6 +50,8 @@ > > #define AMD_PSTATE_TRANSITION_LATENCY 20000 > #define AMD_PSTATE_TRANSITION_DELAY 1000 > +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 > +#define AMD_PSTATE_MAX_CPPC_PERF 255 > > /* > * TODO: We need more time to fine tune processors with shared memory solution > @@ -65,6 +68,9 @@ static struct cpufreq_driver amd_pstate_epp_driver; > static int cppc_state = AMD_PSTATE_UNDEFINED; > static bool cppc_enabled; > > +/*Preferred Core featue is supported*/ > +static bool prefcore = true; > + > /* > * AMD Energy Preference Performance (EPP) > * The EPP is used in the CCLK DPM controller to drive > @@ -290,23 +296,21 @@ static inline int amd_pstate_enable(bool enable) > static int pstate_init_perf(struct amd_cpudata *cpudata) > { > u64 cap1; > - u32 highest_perf; > > int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, > &cap1); > if (ret) > return ret; > > - /* > - * TODO: Introduce AMD specific power feature. > - * > - * CPPC entry doesn't indicate the highest performance in some ASICs. > + /* For platforms that do not support the preferred core feature, the > + * highest_pef may be configured with 166 or 255, to avoid max frequency > + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as > + * the default max perf. > */ > - highest_perf = amd_get_highest_perf(); > - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) > - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); > - > - WRITE_ONCE(cpudata->highest_perf, highest_perf); > + if (prefcore) > + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); > + else > + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); > > WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); > WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); > @@ -318,17 +322,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) > static int cppc_init_perf(struct amd_cpudata *cpudata) > { > struct cppc_perf_caps cppc_perf; > - u32 highest_perf; > > int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); > if (ret) > return ret; > > - highest_perf = amd_get_highest_perf(); > - if (highest_perf > cppc_perf.highest_perf) > - highest_perf = cppc_perf.highest_perf; > - > - WRITE_ONCE(cpudata->highest_perf, highest_perf); > + if (prefcore) > + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); > + else > + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); > > WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); > WRITE_ONCE(cpudata->lowest_nonlinear_perf, > @@ -676,6 +678,72 @@ static void amd_perf_ctl_reset(unsigned int cpu) > wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); > } > > +/* > + * Set AMD Pstate Preferred Core enable can't be done directly from cpufreq callbacks > + * due to locking, so queue the work for later. > + */ > +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) > +{ > + sched_set_itmt_support(); > +} > +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); > + > +/** > + * Get the highest performance register value. > + * @cpu: CPU from which to get highest performance. > + * @highest_perf: Return address. > + * > + * Return: 0 for success, -EIO otherwise. > + */ > +static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf) > +{ > + int ret; > + > + if (boot_cpu_has(X86_FEATURE_CPPC)) { > + u64 cap1; > + > + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); > + if (ret) > + return ret; > + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); > + } else { > + ret = cppc_get_highest_perf(cpu, highest_perf); > + } > + > + return (ret); > +} > + > +static void amd_pstate_init_prefcore(void) > +{ > + int cpu, ret; > + u64 highest_perf; > + > + if (!prefcore) > + return; > + > + for_each_online_cpu(cpu) { > + ret = amd_pstate_get_highest_perf(cpu, &highest_perf); > + if (ret) > + break; > + > + sched_set_itmt_core_prio(highest_perf, cpu); > + > + /* check if CPPC preferred core feature is enabled*/ > + if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) { > + prefcore = false; > + return; > + } > + } > + > + /* > + * This code can be run during CPU online under the > + * CPU hotplug locks, so sched_set_amd_prefcore_support() > + * cannot be called from here. Queue up a work item > + * to invoke it. > + */ > + schedule_work(&sched_prefcore_work); > +} > + > static int amd_pstate_cpu_init(struct cpufreq_policy *policy) > { > int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; > @@ -1037,6 +1105,12 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, > return ret < 0 ? ret : count; > } > > +static ssize_t prefcore_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled"); > +} > + > cpufreq_freq_attr_ro(amd_pstate_max_freq); > cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); > > @@ -1044,6 +1118,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); > cpufreq_freq_attr_rw(energy_performance_preference); > cpufreq_freq_attr_ro(energy_performance_available_preferences); > static DEVICE_ATTR_RW(status); > +static DEVICE_ATTR_RO(prefcore); > > static struct freq_attr *amd_pstate_attr[] = { > &amd_pstate_max_freq, > @@ -1063,6 +1138,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { > > static struct attribute *pstate_global_attributes[] = { > &dev_attr_status.attr, > + &dev_attr_prefcore.attr, > NULL > }; > > @@ -1506,6 +1582,8 @@ static int __init amd_pstate_init(void) > } > } > > + amd_pstate_init_prefcore(); > + > return ret; > > global_attr_free: > @@ -1527,7 +1605,17 @@ static int __init amd_pstate_param(char *str) > > return amd_pstate_set_driver(mode_idx); > } > + > +static int __init amd_prefcore_param(char *str) > +{ > + if (!strcmp(str, "disable")) > + prefcore = false; You know, the prefercore is a hardware capacity, so we should have a way to detect current processor whether it's supported. E.X. whether we can read highest_perf value is AMD_PSTATE_PREFCORE_THRESHOLD or less than AMD_PSTATE_MAX_CPPC_PERF, then set the prefcore enabled. Thanks, Ray > + > + return 0; > +} > + > early_param("amd_pstate", amd_pstate_param); > +early_param("amd_prefcore", amd_prefcore_param); > > MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>"); > MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); > -- > 2.34.1 >
Hi Meng, kernel test robot noticed the following build warnings: [auto build test WARNING on rafael-pm/linux-next] [also build test WARNING on linus/master v6.5 next-20230829] [cannot apply to tip/x86/core] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Meng-Li/x86-Drop-CPU_SUP_INTEL-from-SCHED_MC_PRIO-for-the-expansion/20230829-144723 base: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next patch link: https://lore.kernel.org/r/20230829064340.1136448-4-li.meng%40amd.com patch subject: [PATCH V4 3/7] cpufreq: amd-pstate: Enable AMD Pstate Preferred Core Supporting. config: x86_64-randconfig-r005-20230829 (https://download.01.org/0day-ci/archive/20230829/202308292233.XhcXfvSm-lkp@intel.com/config) compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230829/202308292233.XhcXfvSm-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202308292233.XhcXfvSm-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/cpufreq/amd-pstate.c:692: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Get the highest performance register value. vim +692 drivers/cpufreq/amd-pstate.c 690 691 /** > 692 * Get the highest performance register value. 693 * @cpu: CPU from which to get highest performance. 694 * @highest_perf: Return address. 695 * 696 * Return: 0 for success, -EIO otherwise. 697 */ 698 static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf) 699 { 700 int ret; 701 702 if (boot_cpu_has(X86_FEATURE_CPPC)) { 703 u64 cap1; 704 705 ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); 706 if (ret) 707 return ret; 708 WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); 709 } else { 710 ret = cppc_get_highest_perf(cpu, highest_perf); 711 } 712 713 return (ret); 714 } 715
[AMD Official Use Only - General] Hi Ray: > -----Original Message----- > From: Huang, Ray <Ray.Huang@amd.com> > Sent: Tuesday, August 29, 2023 4:01 PM > To: Meng, Li (Jassmine) <Li.Meng@amd.com> > Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>; linux- > pm@vger.kernel.org; linux-kernel@vger.kernel.org; x86@kernel.org; linux- > acpi@vger.kernel.org; Shuah Khan <skhan@linuxfoundation.org>; linux- > kselftest@vger.kernel.org; Fontenot, Nathan > <Nathan.Fontenot@amd.com>; Sharma, Deepak > <Deepak.Sharma@amd.com>; Deucher, Alexander > <Alexander.Deucher@amd.com>; Limonciello, Mario > <Mario.Limonciello@amd.com>; Huang, Shimmer > <Shimmer.Huang@amd.com>; Yuan, Perry <Perry.Yuan@amd.com>; Du, > Xiaojian <Xiaojian.Du@amd.com>; Viresh Kumar <viresh.kumar@linaro.org>; > Borislav Petkov <bp@alien8.de> > Subject: Re: [PATCH V4 3/7] cpufreq: amd-pstate: Enable AMD Pstate > Preferred Core Supporting. > > On Tue, Aug 29, 2023 at 02:43:36PM +0800, Meng, Li (Jassmine) wrote: > > AMD Pstate driver utilizes the functions and data structures provided > > by the ITMT architecture to enable the scheduler to favor scheduling > > on cores which can be get a higher frequency with lower voltage. We > > call it AMD Pstate Preferrred Core. > > > > Here sched_set_itmt_core_prio() is called to set priorities and > > sched_set_itmt_support() is called to enable ITMT feature. > > AMD Pstate driver uses the highest performance value to indicate the > > priority of CPU. The higher value has a higher priority. > > > > The initial core rankings are set up by AMD Pstate when the system > > boots. > > > > Add device attribute for preferred core states. > > > > Add one new early parameter `enable` to allow user to enable the > > preferred core if the processor and power firmware can support > > preferred core feature. > > > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> > > Co-developed-by: Perry Yuan <Perry.Yuan@amd.com> > > Signed-off-by: Meng Li <li.meng@amd.com> > > Co-developed-by: Meng Li <li.meng@amd.com> > > Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> > > --- > > drivers/cpufreq/amd-pstate.c | 120 > > ++++++++++++++++++++++++++++++----- > > 1 file changed, 104 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/cpufreq/amd-pstate.c > > b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..d02305675f66 100644 > > --- a/drivers/cpufreq/amd-pstate.c > > +++ b/drivers/cpufreq/amd-pstate.c > > @@ -37,6 +37,7 @@ > > #include <linux/uaccess.h> > > #include <linux/static_call.h> > > #include <linux/amd-pstate.h> > > +#include <linux/topology.h> > > > > #include <acpi/processor.h> > > #include <acpi/cppc_acpi.h> > > @@ -49,6 +50,8 @@ > > > > #define AMD_PSTATE_TRANSITION_LATENCY 20000 > > #define AMD_PSTATE_TRANSITION_DELAY 1000 > > +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 > > +#define AMD_PSTATE_MAX_CPPC_PERF 255 > > > > /* > > * TODO: We need more time to fine tune processors with shared memory > > solution @@ -65,6 +68,9 @@ static struct cpufreq_driver > > amd_pstate_epp_driver; static int cppc_state = > AMD_PSTATE_UNDEFINED; > > static bool cppc_enabled; > > > > +/*Preferred Core featue is supported*/ static bool prefcore = true; > > + > > /* > > * AMD Energy Preference Performance (EPP) > > * The EPP is used in the CCLK DPM controller to drive @@ -290,23 > > +296,21 @@ static inline int amd_pstate_enable(bool enable) static > > int pstate_init_perf(struct amd_cpudata *cpudata) { > > u64 cap1; > > - u32 highest_perf; > > > > int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, > > &cap1); > > if (ret) > > return ret; > > > > - /* > > - * TODO: Introduce AMD specific power feature. > > - * > > - * CPPC entry doesn't indicate the highest performance in some > ASICs. > > + /* For platforms that do not support the preferred core feature, the > > + * highest_pef may be configured with 166 or 255, to avoid max > frequency > > + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) > value as > > + * the default max perf. > > */ > > - highest_perf = amd_get_highest_perf(); > > - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) > > - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); > > - > > - WRITE_ONCE(cpudata->highest_perf, highest_perf); > > + if (prefcore) > > + WRITE_ONCE(cpudata->highest_perf, > AMD_PSTATE_PREFCORE_THRESHOLD); > > + else > > + WRITE_ONCE(cpudata->highest_perf, > AMD_CPPC_HIGHEST_PERF(cap1)); > > > > WRITE_ONCE(cpudata->nominal_perf, > AMD_CPPC_NOMINAL_PERF(cap1)); > > WRITE_ONCE(cpudata->lowest_nonlinear_perf, > > AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +322,15 @@ static int > > pstate_init_perf(struct amd_cpudata *cpudata) static int > > cppc_init_perf(struct amd_cpudata *cpudata) { > > struct cppc_perf_caps cppc_perf; > > - u32 highest_perf; > > > > int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); > > if (ret) > > return ret; > > > > - highest_perf = amd_get_highest_perf(); > > - if (highest_perf > cppc_perf.highest_perf) > > - highest_perf = cppc_perf.highest_perf; > > - > > - WRITE_ONCE(cpudata->highest_perf, highest_perf); > > + if (prefcore) > > + WRITE_ONCE(cpudata->highest_perf, > AMD_PSTATE_PREFCORE_THRESHOLD); > > + else > > + WRITE_ONCE(cpudata->highest_perf, > cppc_perf.highest_perf); > > > > WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); > > WRITE_ONCE(cpudata->lowest_nonlinear_perf, > > @@ -676,6 +678,72 @@ static void amd_perf_ctl_reset(unsigned int cpu) > > wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } > > > > +/* > > + * Set AMD Pstate Preferred Core enable can't be done directly from > > +cpufreq callbacks > > + * due to locking, so queue the work for later. > > + */ > > +static void amd_pstste_sched_prefcore_workfn(struct work_struct > > +*work) { > > + sched_set_itmt_support(); > > +} > > +static DECLARE_WORK(sched_prefcore_work, > > +amd_pstste_sched_prefcore_workfn); > > + > > +/** > > + * Get the highest performance register value. > > + * @cpu: CPU from which to get highest performance. > > + * @highest_perf: Return address. > > + * > > + * Return: 0 for success, -EIO otherwise. > > + */ > > +static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf) { > > + int ret; > > + > > + if (boot_cpu_has(X86_FEATURE_CPPC)) { > > + u64 cap1; > > + > > + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); > > + if (ret) > > + return ret; > > + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); > > + } else { > > + ret = cppc_get_highest_perf(cpu, highest_perf); > > + } > > + > > + return (ret); > > +} > > + > > +static void amd_pstate_init_prefcore(void) { > > + int cpu, ret; > > + u64 highest_perf; > > + > > + if (!prefcore) > > + return; > > + > > + for_each_online_cpu(cpu) { > > + ret = amd_pstate_get_highest_perf(cpu, &highest_perf); > > + if (ret) > > + break; > > + > > + sched_set_itmt_core_prio(highest_perf, cpu); > > + > > + /* check if CPPC preferred core feature is enabled*/ > > + if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) { > > + prefcore = false; > > + return; > > + } > > + } > > + > > + /* > > + * This code can be run during CPU online under the > > + * CPU hotplug locks, so sched_set_amd_prefcore_support() > > + * cannot be called from here. Queue up a work item > > + * to invoke it. > > + */ > > + schedule_work(&sched_prefcore_work); > > +} > > + > > static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { > > int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; > @@ > > -1037,6 +1105,12 @@ static ssize_t status_store(struct device *a, struct > device_attribute *b, > > return ret < 0 ? ret : count; > > } > > > > +static ssize_t prefcore_show(struct device *dev, > > + struct device_attribute *attr, char *buf) { > > + return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled"); } > > + > > cpufreq_freq_attr_ro(amd_pstate_max_freq); > > cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); > > > > @@ -1044,6 +1118,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); > > cpufreq_freq_attr_rw(energy_performance_preference); > > cpufreq_freq_attr_ro(energy_performance_available_preferences); > > static DEVICE_ATTR_RW(status); > > +static DEVICE_ATTR_RO(prefcore); > > > > static struct freq_attr *amd_pstate_attr[] = { > > &amd_pstate_max_freq, > > @@ -1063,6 +1138,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = > > { > > > > static struct attribute *pstate_global_attributes[] = { > > &dev_attr_status.attr, > > + &dev_attr_prefcore.attr, > > NULL > > }; > > > > @@ -1506,6 +1582,8 @@ static int __init amd_pstate_init(void) > > } > > } > > > > + amd_pstate_init_prefcore(); > > + > > return ret; > > > > global_attr_free: > > @@ -1527,7 +1605,17 @@ static int __init amd_pstate_param(char *str) > > > > return amd_pstate_set_driver(mode_idx); } > > + > > +static int __init amd_prefcore_param(char *str) { > > + if (!strcmp(str, "disable")) > > + prefcore = false; > > You know, the prefercore is a hardware capacity, so we should have a way to > detect current processor whether it's supported. E.X. whether we can read > highest_perf value is AMD_PSTATE_PREFCORE_THRESHOLD or less than > AMD_PSTATE_MAX_CPPC_PERF, then set the prefcore enabled. > > Thanks, > Ray > [Meng, Li (Jassmine)] Yes, you are right. Here we only provide an interface for users to disable preferred core. Default platform enables preferred core if HW supports this feature. When HW doesn't support this feature, the variable "prefcore" will be set false. Only when Hw support preferred core and users set "enable", , the variable "prefcore" will be set true. > > + > > + return 0; > > +} > > + > > early_param("amd_pstate", amd_pstate_param); > > +early_param("amd_prefcore", amd_prefcore_param); > > > > MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>"); > > MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); > > -- > > 2.34.1 > >
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..d02305675f66 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -37,6 +37,7 @@ #include <linux/uaccess.h> #include <linux/static_call.h> #include <linux/amd-pstate.h> +#include <linux/topology.h> #include <acpi/processor.h> #include <acpi/cppc_acpi.h> @@ -49,6 +50,8 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 +#define AMD_PSTATE_MAX_CPPC_PERF 255 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -65,6 +68,9 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +/*Preferred Core featue is supported*/ +static bool prefcore = true; + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -290,23 +296,21 @@ static inline int amd_pstate_enable(bool enable) static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; - u32 highest_perf; int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; - /* - * TODO: Introduce AMD specific power feature. - * - * CPPC entry doesn't indicate the highest performance in some ASICs. + /* For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as + * the default max perf. */ - highest_perf = amd_get_highest_perf(); - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +322,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) static int cppc_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; - u32 highest_perf; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - highest_perf = amd_get_highest_perf(); - if (highest_perf > cppc_perf.highest_perf) - highest_perf = cppc_perf.highest_perf; - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, @@ -676,6 +678,72 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } +/* + * Set AMD Pstate Preferred Core enable can't be done directly from cpufreq callbacks + * due to locking, so queue the work for later. + */ +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); + +/** + * Get the highest performance register value. + * @cpu: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf) +{ + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 cap1; + + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + } else { + ret = cppc_get_highest_perf(cpu, highest_perf); + } + + return (ret); +} + +static void amd_pstate_init_prefcore(void) +{ + int cpu, ret; + u64 highest_perf; + + if (!prefcore) + return; + + for_each_online_cpu(cpu) { + ret = amd_pstate_get_highest_perf(cpu, &highest_perf); + if (ret) + break; + + sched_set_itmt_core_prio(highest_perf, cpu); + + /* check if CPPC preferred core feature is enabled*/ + if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) { + prefcore = false; + return; + } + } + + /* + * This code can be run during CPU online under the + * CPU hotplug locks, so sched_set_amd_prefcore_support() + * cannot be called from here. Queue up a work item + * to invoke it. + */ + schedule_work(&sched_prefcore_work); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -1037,6 +1105,12 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static ssize_t prefcore_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%s\n", prefcore ? "enabled" : "disabled"); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -1044,6 +1118,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RO(prefcore); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -1063,6 +1138,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_prefcore.attr, NULL }; @@ -1506,6 +1582,8 @@ static int __init amd_pstate_init(void) } } + amd_pstate_init_prefcore(); + return ret; global_attr_free: @@ -1527,7 +1605,17 @@ static int __init amd_pstate_param(char *str) return amd_pstate_set_driver(mode_idx); } + +static int __init amd_prefcore_param(char *str) +{ + if (!strcmp(str, "disable")) + prefcore = false; + + return 0; +} + early_param("amd_pstate", amd_pstate_param); +early_param("amd_prefcore", amd_prefcore_param); MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>"); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");