From patchwork Fri Sep 22 11:51:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 13395665 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76579E7D0CA for ; Fri, 22 Sep 2023 11:51:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233955AbjIVLvl (ORCPT ); Fri, 22 Sep 2023 07:51:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233939AbjIVLvi (ORCPT ); Fri, 22 Sep 2023 07:51:38 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB3A618F; Fri, 22 Sep 2023 04:51:31 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38MAmHM7014092; Fri, 22 Sep 2023 11:51:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=oZAGi+S5+oLGAe34keXzAUhRqBkFJkaTZyh/xFhj3OE=; b=CIl6my2gJjJWttM0+VD+0HUIJuT9OqPg+5GnajTM8lPYcLRfLLZWhmWMCR9LP+uRiSB6 5866tT5qbxKTLmuRzXlKHhadkvM/3gDTWxQRzfDF+OboOb/mQNC3zeG0Wp9+b3n0laaC DB9Q4uXT/hX+xQFoKbJuQZHr7zKvDe3nNF6eYIL32xBP/0egyGgI4WxnVRMM0uN0gEjL dKLdU2SDTC5lfmLbtc6xokaa3kXBOEZ2ifuw6QqJU5eCfY9ze4vnKRrst2TUtCzGH3Zg FhCdDl/R3N4kgSb3rnJLzw8d6/kZSfLIP58utC6s5Jxx+swxRoA6PWYa+1pSIwJOqqtY ag== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t8txg9smy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:21 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 38MBoaDE027187; Fri, 22 Sep 2023 11:51:18 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3t55emancc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:18 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 38MBpHxS027859; Fri, 22 Sep 2023 11:51:17 GMT Received: from win-platform-upstream01.qualcomm.com (win-platform-upstream01.qualcomm.com [10.242.182.84]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 38MBpHP2027855 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 11:51:17 +0000 Received: by win-platform-upstream01.qualcomm.com (Postfix, from userid 330701) id 927559A7; Fri, 22 Sep 2023 17:21:16 +0530 (IST) From: Sricharan R To: krzysztof.kozlowski@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, srinivas.kandagatla@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dmitry.baryshkov@linaro.org, quic_srichara@quicinc.com Subject: [PATCH V3 4/4] arm64: dts: qcom: ipq5018: Add tsens node Date: Fri, 22 Sep 2023 17:21:16 +0530 Message-Id: <20230922115116.2748804-5-srichara@win-platform-upstream01.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> References: <20230922115116.2748804-1-srichara@win-platform-upstream01.qualcomm.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: pTyb6xxSQuHUDRrYtxiXp5HNgcpja_vq X-Proofpoint-GUID: pTyb6xxSQuHUDRrYtxiXp5HNgcpja_vq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-22_09,2023-09-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 priorityscore=1501 bulkscore=0 spamscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=904 mlxscore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309220100 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Sricharan Ramabadhran IPQ5018 has tsens V1.0 IP with 4 sensors. There is no RPM, so tsens has to be manually enabled. Adding the tsens and nvmem node and IPQ5018 has 4 thermal sensors (zones). With the critical temperature being 120'C and action is to reboot. Adding all the 4 zones here. Signed-off-by: Sricharan Ramabadhran --- [v3] Ordered the qfprom device node properties as per Krzysztof's comments arch/arm64/boot/dts/qcom/ipq5018.dtsi | 169 ++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 9f13d2dcdfd5..9e28b54ebcbd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -93,6 +93,117 @@ soc: soc@0 { #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + qfprom: qfprom@a0000 { + compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; + reg = <0xa0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@249 { + reg = <0x249 2>; + bits = <3 8>; + }; + + tsens_base2: base2@24a { + reg = <0x24a 2>; + bits = <3 8>; + }; + + tsens_mode: mode@249 { + reg = <0x249 1>; + bits = <0 3>; + }; + + tsens_s0_p1: s0-p1@24b { + reg = <0x24b 0x2>; + bits = <2 6>; + }; + + tsens_s0_p2: s0-p2@24c { + reg = <0x24c 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@24c { + reg = <0x24c 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@24d { + reg = <0x24d 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@24e { + reg = <0x24e 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@24f { + reg = <0x24f 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@24f { + reg = <0x24f 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@250 { + reg = <0x250 0x2>; + bits = <5 6>; + }; + + tsens_s4_p1: s4-p1@251 { + reg = <0x251 0x2>; + bits = <3 6>; + }; + + tsens_s4_p2: s4-p2@254 { + reg = <0x254 0x1>; + bits = <0 6>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5018-tsens"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SORT */ + + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, + <&tsens_base2>, + <&tsens_s0_p1>, + <&tsens_s0_p2>, + <&tsens_s1_p1>, + <&tsens_s1_p2>, + <&tsens_s2_p1>, + <&tsens_s2_p2>, + <&tsens_s3_p1>, + <&tsens_s3_p2>, + <&tsens_s4_p1>, + <&tsens_s4_p2>; + + nvmem-cell-names = "mode", + "base1", + "base2", + "s0_p1", + "s0_p2", + "s1_p1", + "s1_p2", + "s2_p1", + "s2_p2", + "s3_p1", + "s3_p2", + "s4_p1", + "s4_p2"; + + interrupts = ; + interrupt-names = "uplow"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; @@ -240,6 +351,64 @@ frame@b128000 { }; }; + thermal-zones { + ubi32-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 1>; + + trips { + ubi32-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + top_glue-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + + gephy-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + gephy-critical { + temperature = <120000>; + hysteresis = <2>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = ,