From patchwork Thu Dec 21 03:50:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13501057 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B18D45249; Thu, 21 Dec 2023 03:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="cIGOmNmb" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BL2RrVT028351; Thu, 21 Dec 2023 03:50:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=8cQR0bgH4ekU1zZfVJJ3KFyRZ0SmaEyRsEKEDKifM6g =; b=cIGOmNmbN6XzCrkkVLTQPN5FWGFrH2JnS4ODVyoVjJtSy3V1I6gxTlvlfS1 8Cr38029PUj8yW9z7RtTM5pWF/TH54i/28HitCF90mBJqi6b9WJI4FQ6a1gbRIMc Jl0hysktuNC7PQ8vedcxVGaFuGcyqX+kadogK6qy9FY+J99kI+RbHRl0jjSlw+86 N8FKxpC+P2I9Goj5Ro2kdRcn1CCeFYp+3krKi+jbnwZFVKajkkNU99M/YIlouFxi 49L1TEcdbAlyvrQVGUCtsrxoq1r3aMnpZKa4Nv5G/HnxYWKk8jYRddo+SeQTPwb9 MzHIe9mduRka6vxW5Q4vWDaNPlg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v3tnw33aq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:51 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BL3oonV011706 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:50 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 19:50:50 -0800 From: Bjorn Andersson Date: Wed, 20 Dec 2023 19:50:36 -0800 Subject: [PATCH 2/8] clk: qcom: gdsc: Enable supply reglator in GPU GX handler Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231220-sa8295p-gpu-v1-2-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> In-Reply-To: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Ulf Hansson , Johan Hovold , "Catalin Marinas" , Will Deacon CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703130649; l=1170; i=quic_bjorande@quicinc.com; s=20230915; h=from:subject:message-id; bh=NRcjjCsDovL9I1ze2bc9Mx0aQssR4APji3KJJF2CHFc=; b=+IIJYZC7MtZAIxx8g+S8H7rfx+fxUQ/rQ/1F9o5CXT11uGqEfmW5vC6m8i11QxyUkdh0etMIcUMz uio/xpvfBuxjbWu7NwmGTrLqPUEXJ1zLkU7lGam7BCiU4Nx16kvD X-Developer-Key: i=quic_bjorande@quicinc.com; a=ed25519; pk=VkhObtljigy9k0ZUIE1Mvr0Y+E1dgBEH9WoLQnUtbIM= X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: msi8icBqaIBCMa-5gcEzsM1rMbyGclam X-Proofpoint-ORIG-GUID: msi8icBqaIBCMa-5gcEzsM1rMbyGclam X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 mlxlogscore=976 lowpriorityscore=0 adultscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312210025 The GX GDSC is modelled to aid the GMU in powering down the GPU in the event that the GPU crashes, so that it can be restarted again. But in the event that the power-domain is supplied through a dedicated regulator (in contrast to being a subdomin of another power-domain), something needs to turn that regulator on, both to make sure things are powered and to match the operation in gdsc_disable(). Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gdsc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 5358e28122ab..d1139c895503 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -557,7 +557,13 @@ void gdsc_unregister(struct gdsc_desc *desc) */ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) { + struct gdsc *sc = domain_to_gdsc(domain); + int ret = 0; + /* Do nothing but give genpd the impression that we were successful */ - return 0; + if (sc->rsupply) + ret = regulator_enable(sc->rsupply); + + return ret; } EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);