| Message ID | 20231220-sa8295p-gpu-v1-7-d8cdf2257f97@quicinc.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | arm64: dts: qcom: sa8295p: Enable GPU | expand |
On Thu, 21 Dec 2023 at 05:52, Bjorn Andersson <quic_bjorande@quicinc.com> wrote: > > With the necessary support in place for supplying VDD_GFX from the > MAX20411 regulator, enable the GPU clock controller, GMU, Adreno SMMU > and the GPU on the SA8295P ADP. > > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > index e16406c9c19d..7775c5f4d2e8 100644 > --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts > @@ -108,6 +108,13 @@ edp3_connector_in: endpoint { > }; > }; > }; > + > + reserved-memory { > + gpu_mem: gpu-mem@8bf00000 { > + reg = <0 0x8bf00000 0 0x2000>; > + no-map; > + }; > + }; > }; > > &apps_rsc { > @@ -286,6 +293,28 @@ vdd_gfx: regulator@39 { > }; > }; > > +&gpucc { > + vdd-gfx-supply = <&vdd_gfx>; > + status = "okay"; > +}; > + > +&gmu { > + status = "okay"; > +}; > + > +&gpu { > + status = "okay"; > + > + zap-shader { > + memory-region = <&gpu_mem>; > + firmware-name = "qcom/sa8295p/a690_zap.mdt"; Can we please have .mbn here? Other than that, it looks good to me. > + }; > +}; > + > +&gpu_smmu { > + status = "okay"; > +}; > + > &mdss0 { > status = "okay"; > }; > > -- > 2.25.1 > >
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index e16406c9c19d..7775c5f4d2e8 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -108,6 +108,13 @@ edp3_connector_in: endpoint { }; }; }; + + reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + }; }; &apps_rsc { @@ -286,6 +293,28 @@ vdd_gfx: regulator@39 { }; }; +&gpucc { + vdd-gfx-supply = <&vdd_gfx>; + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sa8295p/a690_zap.mdt"; + }; +}; + +&gpu_smmu { + status = "okay"; +}; + &mdss0 { status = "okay"; };
With the necessary support in place for supplying VDD_GFX from the MAX20411 regulator, enable the GPU clock controller, GMU, Adreno SMMU and the GPU on the SA8295P ADP. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)