diff mbox series

[1/2] dt-bindings: interconnect: Add Qualcomm IPQ9574 support

Message ID 20240321043149.2739204-2-quic_varada@quicinc.com (mailing list archive)
State Handled Elsewhere, archived
Headers show
Series Add interconnect driver for IPQ9574 SoC | expand

Commit Message

Varadarajan Narayanan March 21, 2024, 4:31 a.m. UTC 
Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
interfaces. This will be used by the gcc-ipq9574 driver
that will for providing interconnect services using the
icc-clk framework.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 .../dt-bindings/interconnect/qcom,ipq9574.h   | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h

Comments

Krzysztof Kozlowski March 21, 2024, 7:23 a.m. UTC | #1 
On 21/03/2024 05:31, Varadarajan Narayanan wrote:
> Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
> interfaces. This will be used by the gcc-ipq9574 driver
> that will for providing interconnect services using the
> icc-clk framework.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>  .../dt-bindings/interconnect/qcom,ipq9574.h   | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
> 
> diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
> new file mode 100644
> index 000000000000..96f79a86e8d2
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
> @@ -0,0 +1,62 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +#ifndef INTERCONNECT_QCOM_IPQ9574_H
> +#define INTERCONNECT_QCOM_IPQ9574_H
> +
> +#define IPQ_APPS_ID			9574	/* some unique value */
> +#define IPQ_NSS_ID			(IPQ_APPS_ID * 2)
> +
> +#define IPQ_ANOC_PCIE0_1_MAS		0
> +#define IPQ_ANOC_PCIE0_1_SLV		1

Please use style matching rest of mainline code. There is no IPQ in the
name of interconnect. Open recent SM8650 or similar and see.

Best regards,
Krzysztof
Varadarajan Narayanan March 21, 2024, 9:57 a.m. UTC | #2 
On Thu, Mar 21, 2024 at 08:23:01AM +0100, Krzysztof Kozlowski wrote:
> On 21/03/2024 05:31, Varadarajan Narayanan wrote:
> > Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
> > interfaces. This will be used by the gcc-ipq9574 driver
> > that will for providing interconnect services using the
> > icc-clk framework.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> >  .../dt-bindings/interconnect/qcom,ipq9574.h   | 62 +++++++++++++++++++
> >  1 file changed, 62 insertions(+)
> >  create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
> >
> > diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
> > new file mode 100644
> > index 000000000000..96f79a86e8d2
> > --- /dev/null
> > +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
> > @@ -0,0 +1,62 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> > +#ifndef INTERCONNECT_QCOM_IPQ9574_H
> > +#define INTERCONNECT_QCOM_IPQ9574_H
> > +
> > +#define IPQ_APPS_ID			9574	/* some unique value */
> > +#define IPQ_NSS_ID			(IPQ_APPS_ID * 2)
> > +
> > +#define IPQ_ANOC_PCIE0_1_MAS		0
> > +#define IPQ_ANOC_PCIE0_1_SLV		1
>
> Please use style matching rest of mainline code. There is no IPQ in the
> name of interconnect. Open recent SM8650 or similar and see.

Ok. Will update and post the next version.

Thanks
Varada
Rob Herring (Arm) March 21, 2024, 2:35 p.m. UTC | #3 
On Thu, Mar 21, 2024 at 10:01:48AM +0530, Varadarajan Narayanan wrote:
> Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
> interfaces. This will be used by the gcc-ipq9574 driver
> that will for providing interconnect services using the
> icc-clk framework.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>  .../dt-bindings/interconnect/qcom,ipq9574.h   | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>  create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
> 
> diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
> new file mode 100644
> index 000000000000..96f79a86e8d2
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
> @@ -0,0 +1,62 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

Where did you come up with GPL-2.0+? Every other qcom interconnect 
header is GPL-2.0-only. Is your employer okay with GPLv3 AND after?

Rob
Varadarajan Narayanan March 21, 2024, 3:50 p.m. UTC | #4 
On Thu, Mar 21, 2024 at 09:35:49AM -0500, Rob Herring wrote:
> On Thu, Mar 21, 2024 at 10:01:48AM +0530, Varadarajan Narayanan wrote:
> > Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
> > interfaces. This will be used by the gcc-ipq9574 driver
> > that will for providing interconnect services using the
> > icc-clk framework.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> >  .../dt-bindings/interconnect/qcom,ipq9574.h   | 62 +++++++++++++++++++
> >  1 file changed, 62 insertions(+)
> >  create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
> >
> > diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
> > new file mode 100644
> > index 000000000000..96f79a86e8d2
> > --- /dev/null
> > +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
> > @@ -0,0 +1,62 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>
> Where did you come up with GPL-2.0+? Every other qcom interconnect
> header is GPL-2.0-only. Is your employer okay with GPLv3 AND after?

Oops. Will fix it in the next version.

Thanks
Varada
diff mbox series

Patch

diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
new file mode 100644
index 000000000000..96f79a86e8d2
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
@@ -0,0 +1,62 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+#ifndef INTERCONNECT_QCOM_IPQ9574_H
+#define INTERCONNECT_QCOM_IPQ9574_H
+
+#define IPQ_APPS_ID			9574	/* some unique value */
+#define IPQ_NSS_ID			(IPQ_APPS_ID * 2)
+
+#define IPQ_ANOC_PCIE0_1_MAS		0
+#define IPQ_ANOC_PCIE0_1_SLV		1
+#define IPQ_SNOC_PCIE0_1_MAS		2
+#define IPQ_SNOC_PCIE0_1_SLV		3
+#define IPQ_ANOC_PCIE1_1_MAS		4
+#define IPQ_ANOC_PCIE1_1_SLV		5
+#define IPQ_SNOC_PCIE1_1_MAS		6
+#define IPQ_SNOC_PCIE1_1_SLV		7
+#define IPQ_ANOC_PCIE2_2_MAS		8
+#define IPQ_ANOC_PCIE2_2_SLV		9
+#define IPQ_SNOC_PCIE2_2_MAS		10
+#define IPQ_SNOC_PCIE2_2_SLV		11
+#define IPQ_ANOC_PCIE3_2_MAS		12
+#define IPQ_ANOC_PCIE3_2_SLV		13
+#define IPQ_SNOC_PCIE3_2_MAS		14
+#define IPQ_SNOC_PCIE3_2_SLV		15
+#define IPQ_USB_MAS			16
+#define IPQ_USB_SLV			17
+#define IPQ_USB_AXI_MAS			18
+#define IPQ_USB_AXI_SLV			19
+#define IPQ_NSSNOC_NSSCC_MAS		20
+#define IPQ_NSSNOC_NSSCC_SLV		21
+#define IPQ_NSSNOC_SNOC_MAS		22
+#define IPQ_NSSNOC_SNOC_SLV		23
+#define IPQ_NSSNOC_SNOC_1_MAS		24
+#define IPQ_NSSNOC_SNOC_1_SLV		25
+#define IPQ_NSSNOC_PCNOC_1_MAS		26
+#define IPQ_NSSNOC_PCNOC_1_SLV		27
+#define IPQ_NSSNOC_QOSGEN_REF_MAS	28
+#define IPQ_NSSNOC_QOSGEN_REF_SLV	29
+#define IPQ_NSSNOC_TIMEOUT_REF_MAS	30
+#define IPQ_NSSNOC_TIMEOUT_REF_SLV	31
+#define IPQ_NSSNOC_XO_DCD_MAS		32
+#define IPQ_NSSNOC_XO_DCD_SLV		33
+#define IPQ_NSSNOC_ATB_MAS		34
+#define IPQ_NSSNOC_ATB_SLV		35
+#define IPQ_MEM_NOC_NSSNOC_MAS		36
+#define IPQ_MEM_NOC_NSSNOC_SLV		37
+#define IPQ_NSSNOC_MEMNOC_MAS		38
+#define IPQ_NSSNOC_MEMNOC_SLV		39
+#define IPQ_NSSNOC_MEM_NOC_1_MAS	40
+#define IPQ_NSSNOC_MEM_NOC_1_SLV	41
+
+#define IPQ_NSS_CC_NSSNOC_PPE_MAS	0
+#define IPQ_NSS_CC_NSSNOC_PPE_SLV	1
+#define IPQ_NSS_CC_NSSNOC_PPE_CFG_MAS	2
+#define IPQ_NSS_CC_NSSNOC_PPE_CFG_SLV	3
+#define IPQ_NSS_CC_NSSNOC_NSS_CSR_MAS	4
+#define IPQ_NSS_CC_NSSNOC_NSS_CSR_SLV	5
+#define IPQ_NSS_CC_NSSNOC_IMEM_QSB_MAS	6
+#define IPQ_NSS_CC_NSSNOC_IMEM_QSB_SLV	7
+#define IPQ_NSS_CC_NSSNOC_IMEM_AHB_MAS	8
+#define IPQ_NSS_CC_NSSNOC_IMEM_AHB_SLV	9
+
+#endif /* INTERCONNECT_QCOM_IPQ9574_H */