| Message ID | 20240326114743.712167-8-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | viresh kumar |
| Headers | show |
| Series | cpufreq: sun50i: Add Allwinner H616 support | expand |
Dne torek, 26. marec 2024 ob 12:47:42 CET je Andre Przywara napisal(a): > From: Martin Botka <martin.botka@somainline.org> > > Add an Operating Performance Points table for the CPU cores to enable > Dynamic Voltage & Frequency Scaling (DVFS) on the H616. > The values were taken from the BSP sources. The (newer) H700 chips we > have seen seem to use a separate speed bin, its OPP values were taken > from a live system and added to the mix. > > Also add the needed cpu_speed_grade nvmem cell and the cooling cells > properties, to enable passive cooling. > > Signed-off-by: Martin Botka <martin.botka@somainline.org> > [Andre: rework to minimise opp-microvolt properties] > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > .../dts/allwinner/sun50i-h616-cpu-opp.dtsi | 125 ++++++++++++++++++ > .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 8 ++ > 2 files changed, 133 insertions(+) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi > new file mode 100644 > index 0000000000000..6073fdf672592 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi > @@ -0,0 +1,125 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +// Copyright (C) 2023 Martin Botka <martin@somainline.org> > + > +/ { > + cpu_opp_table: opp-table-cpu { > + compatible = "allwinner,sun50i-h616-operating-points"; > + nvmem-cells = <&cpu_speed_grade>; > + opp-shared; > + > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + opp-microvolt = <900000>; Ideally triplet of voltages should be specified, to support PMIC-less boards, but that's unlikely to happen with these SoCs. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x3f>; > + }; > + > + opp-600000000 { > + opp-hz = /bits/ 64 <600000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x12>; > + }; > + > + opp-720000000 { > + opp-hz = /bits/ 64 <720000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x2d>; > + }; > + > + opp-792000000 { > + opp-hz = /bits/ 64 <792000000>; > + opp-microvolt-speed1 = <900000>; > + opp-microvolt-speed4 = <940000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x12>; > + }; > + > + opp-936000000 { > + opp-hz = /bits/ 64 <936000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x0d>; > + }; > + > + opp-1008000000 { > + opp-hz = /bits/ 64 <1008000000>; > + opp-microvolt-speed0 = <950000>; > + opp-microvolt-speed1 = <940000>; > + opp-microvolt-speed2 = <950000>; > + opp-microvolt-speed3 = <950000>; > + opp-microvolt-speed4 = <1020000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x1f>; > + }; > + > + opp-10320000 { > + opp-hz = /bits/ 64 <1032000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x20>; > + }; > + > + opp-1104000000 { > + opp-hz = /bits/ 64 <1104000000>; > + opp-microvolt-speed0 = <1000000>; > + opp-microvolt-speed2 = <1000000>; > + opp-microvolt-speed3 = <1000000>; > + opp-microvolt-speed5 = <950000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x2d>; > + }; > + > + opp-1200000000 { > + opp-hz = /bits/ 64 <1200000000>; > + opp-microvolt-speed0 = <1050000>; > + opp-microvolt-speed1 = <1020000>; > + opp-microvolt-speed2 = <1050000>; > + opp-microvolt-speed3 = <1050000>; > + opp-microvolt-speed4 = <1100000>; > + opp-microvolt-speed5 = <1020000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x3f>; > + }; > + > + opp-1320000000 { > + opp-hz = /bits/ 64 <1320000000>; > + opp-microvolt = <1100000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x1d>; > + }; > + > + opp-1416000000 { > + opp-hz = /bits/ 64 <1416000000>; > + opp-microvolt = <1100000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x2d>; > + }; > + > + opp-1512000000 { > + opp-hz = /bits/ 64 <1512000000>; > + opp-microvolt-speed1 = <1100000>; > + opp-microvolt-speed3 = <1100000>; > + opp-microvolt-speed5 = <1160000>; > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-supported-hw = <0x2a>; > + }; > + }; > +}; > + > +&cpu0 { > + operating-points-v2 = <&cpu_opp_table>; > +}; > + > +&cpu1 { > + operating-points-v2 = <&cpu_opp_table>; > +}; > + > +&cpu2 { > + operating-points-v2 = <&cpu_opp_table>; > +}; > + > +&cpu3 { > + operating-points-v2 = <&cpu_opp_table>; > +}; > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi > index b2e85e52d1a12..c0fa466fa9f07 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi > @@ -26,6 +26,7 @@ cpu0: cpu@0 { > reg = <0>; > enable-method = "psci"; > clocks = <&ccu CLK_CPUX>; > + #cooling-cells = <2>; > }; > > cpu1: cpu@1 { > @@ -34,6 +35,7 @@ cpu1: cpu@1 { > reg = <1>; > enable-method = "psci"; > clocks = <&ccu CLK_CPUX>; > + #cooling-cells = <2>; > }; > > cpu2: cpu@2 { > @@ -42,6 +44,7 @@ cpu2: cpu@2 { > reg = <2>; > enable-method = "psci"; > clocks = <&ccu CLK_CPUX>; > + #cooling-cells = <2>; > }; > > cpu3: cpu@3 { > @@ -50,6 +53,7 @@ cpu3: cpu@3 { > reg = <3>; > enable-method = "psci"; > clocks = <&ccu CLK_CPUX>; > + #cooling-cells = <2>; > }; > }; > > @@ -156,6 +160,10 @@ sid: efuse@3006000 { > ths_calibration: thermal-sensor-calibration@14 { > reg = <0x14 0x8>; > }; > + > + cpu_speed_grade: cpu-speed-grade@0 { > + reg = <0x0 2>; > + }; > }; > > watchdog: watchdog@30090a0 { >
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi new file mode 100644 index 0000000000000..6073fdf672592 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2023 Martin Botka <martin@somainline.org> + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "allwinner,sun50i-h616-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x3f>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x12>; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x2d>; + }; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed4 = <940000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x12>; + }; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x0d>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt-speed0 = <950000>; + opp-microvolt-speed1 = <940000>; + opp-microvolt-speed2 = <950000>; + opp-microvolt-speed3 = <950000>; + opp-microvolt-speed4 = <1020000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1f>; + }; + + opp-10320000 { + opp-hz = /bits/ 64 <1032000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x20>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt-speed0 = <1000000>; + opp-microvolt-speed2 = <1000000>; + opp-microvolt-speed3 = <1000000>; + opp-microvolt-speed5 = <950000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x2d>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt-speed0 = <1050000>; + opp-microvolt-speed1 = <1020000>; + opp-microvolt-speed2 = <1050000>; + opp-microvolt-speed3 = <1050000>; + opp-microvolt-speed4 = <1100000>; + opp-microvolt-speed5 = <1020000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x3f>; + }; + + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1d>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x2d>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt-speed1 = <1100000>; + opp-microvolt-speed3 = <1100000>; + opp-microvolt-speed5 = <1160000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x2a>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index b2e85e52d1a12..c0fa466fa9f07 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -26,6 +26,7 @@ cpu0: cpu@0 { reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -34,6 +35,7 @@ cpu1: cpu@1 { reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -42,6 +44,7 @@ cpu2: cpu@2 { reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -50,6 +53,7 @@ cpu3: cpu@3 { reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; }; @@ -156,6 +160,10 @@ sid: efuse@3006000 { ths_calibration: thermal-sensor-calibration@14 { reg = <0x14 0x8>; }; + + cpu_speed_grade: cpu-speed-grade@0 { + reg = <0x0 2>; + }; }; watchdog: watchdog@30090a0 {