From patchwork Wed Apr 17 09:14:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13633082 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD9B4130A43; Wed, 17 Apr 2024 09:14:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713345293; cv=none; b=NshrXoPhieMttO+QUt8tp5aedZ4N96i2E6PCWznTu6Puy1f6xZm4HH+Dm1VB62fkGL8G0vgQ/zaTIa+3wgVAiEnAKOhRt3/9tZMwOMI2sjqKU7/HTcFAdjCYQRky2HRT7SJ+Cso+zrVJfSUJXGTjzAkOYzZiuybW9qWyMpH7AkE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713345293; c=relaxed/simple; bh=xJ47AhVCJnPzfAzCCyTdF9TGxPyIWa3chHq1ZLjt15I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=emw6GebqNbKejznfMsxTG7dv812oEq2P4GeeMGlUvcNnYKh+ayvfqb8Kyc48gdoAzvCb1Pgf/X1EZ6N80nd1+SR8JsS4DFNkVWqYKcEpMU3jyoHEVI4Io8ciObbQyFrrADoaODbPjxwOxNxhuJ0I5FhquUzdePYROBTJ+GmvtSA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=JC27ypqx; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="JC27ypqx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1713345290; bh=xJ47AhVCJnPzfAzCCyTdF9TGxPyIWa3chHq1ZLjt15I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JC27ypqxKniqvPsUjwKo4L0k6DdkgC53msUFdxkR88vCIzAYWlAh3TwfhyuoJyN3c CoFAE7owUWu6Rxi4d3YPEu9tEwCkd/Y0aGAVL5sw3L6mlJzJuDoLLYTTremf7Lv4sH U5DC/1m5ZrREcj+ODMKJ/WjIWvK23PzQFBncS3eKVpBwhyDnIN+IMcje7PMW0GRwVW Lz0pnwLDnZzAocuKWBsGcMz5WZgWGR9Opz3KaTmuxcynbXz9nsCBxIhgCYuQnyViux JXmv/wX6s8BLUCbXYpSp+HU9CAicKsqsL26kYOuiPyt4XAq8HRX0qLGdaKNLxESpuL Jmg7AIZh0qing== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 29C363782145; Wed, 17 Apr 2024 09:14:49 +0000 (UTC) From: AngeloGioacchino Del Regno To: djakov@kernel.org Cc: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, lgirdwood@gmail.com, broonie@kernel.org, keescook@chromium.org, gustavoars@kernel.org, henryc.chen@mediatek.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org, amergnat@baylibre.com Subject: [PATCH v2 3/7] dt-bindings: soc: mediatek: Add DVFSRC bindings for MT8183 and MT8195 Date: Wed, 17 Apr 2024 11:14:38 +0200 Message-ID: <20240417091442.170505-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240417091442.170505-1-angelogioacchino.delregno@collabora.com> References: <20240417091442.170505-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add bindings for the MediaTek Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC), a hardware module used to collect all the requests from both software and the various remote processors embedded into the SoC and decide about a minimum operating voltage and a minimum DRAM frequency to fulfill those requests in an effort to provide the best achievable performance per watt. This hardware IP is capable of transparently performing direct register R/W on all of the DVFSRC-controlled regulators and SoC bandwidth knobs. Signed-off-by: AngeloGioacchino Del Regno --- .../soc/mediatek/mediatek,mt8183-dvfsrc.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml new file mode 100644 index 000000000000..da948098eebe --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8183-dvfsrc.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mt8183-dvfsrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) + +description: + The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a + Hardware module used to collect all the requests from both software and the + various remote processors embedded into the SoC and decide about a minimum + operating voltage and a minimum DRAM frequency to fulfill those requests in + an effort to provide the best achievable performance per watt. + This hardware IP is capable of transparently performing direct register R/W + on all of the DVFSRC-controlled regulators and SoC bandwidth knobs. + +maintainers: + - AngeloGioacchino Del Regno + - Henry Chen + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt8183-dvfsrc + - mediatek,mt8195-dvfsrc + - items: + - const: mediatek,mt8192-dvfsrc + - const: mediatek,mt8195-dvfsrc + + reg: + maxItems: 1 + description: DVFSRC common register address and length. + + '#address-cells': + const: 1 + + '#size-cells': + enum: [ 0, 1 ] + +patternProperties: + "regulators@[0-9a-f]+$": + type: object + $ref: /schemas/regulator/mediatek,mt6873-dvfsrc-regulator.yaml# + + "interconnect@[0-9a-f]+$": + type: object + $ref: /schemas/interconnect/mediatek,mt8183-emi.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-controller@10012000 { + compatible = "mediatek,mt8195-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + regulators@0 { + compatible = "mediatek,mt8195-dvfsrc-regulator"; + reg = <0>; + + dvfsrc_vcore: dvfsrc-vcore { + regulator-name = "dvfsrc-vcore"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + }; + + dvfsrc_vscp: dvfsrc-vscp { + regulator-name = "dvfsrc-vscp"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + }; + }; + + emi_icc: interconnect@1 { + compatible = "mediatek,mt8195-emi"; + reg = <1>; + #interconnect-cells = <1>; + }; + }; + };