| Message ID | 20240618154306.279637-2-quic_sibis@quicinc.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: Enable bwmon support | expand |
On 6/18/24 17:43, Sibi Sankar wrote: > Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4 > instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR > path. Also make the opp-table optional for the X1E cpu-bwmon instances, > since they use the same opp-table between them. > > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- I think we can just drop the opp-table child node from required altogether, bindings shouldn't care about where the OPP table (which is referenced in the operating-points-v2 property) comes from Konrad
On 18/06/2024 18:02, Konrad Dybcio wrote: > > > On 6/18/24 17:43, Sibi Sankar wrote: >> Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4 >> instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR >> path. Also make the opp-table optional for the X1E cpu-bwmon instances, >> since they use the same opp-table between them. >> >> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> >> --- > > I think we can just drop the opp-table child node from required altogether, > bindings shouldn't care about where the OPP table (which is referenced in > the operating-points-v2 property) comes from I agree. Best regards, Krzysztof
On 6/21/24 12:14, Krzysztof Kozlowski wrote: > On 18/06/2024 18:02, Konrad Dybcio wrote: >> >> >> On 6/18/24 17:43, Sibi Sankar wrote: >>> Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4 >>> instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR >>> path. Also make the opp-table optional for the X1E cpu-bwmon instances, >>> since they use the same opp-table between them. >>> >>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> >>> --- >> >> I think we can just drop the opp-table child node from required altogether, >> bindings shouldn't care about where the OPP table (which is referenced in >> the operating-points-v2 property) comes from > > I agree. Thanks, will break ^^ into a separate patch for the next re-spin. -Sibi > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index 05067e197abe..090dbf8dca8b 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -35,6 +35,7 @@ properties: - qcom,sm8250-cpu-bwmon - qcom,sm8550-cpu-bwmon - qcom,sm8650-cpu-bwmon + - qcom,x1e80100-cpu-bwmon - const: qcom,sdm845-bwmon # BWMON v4, unified register space - items: - enum: @@ -44,6 +45,7 @@ properties: - qcom,sm8250-llcc-bwmon - qcom,sm8550-llcc-bwmon - qcom,sm8650-llcc-bwmon + - qcom,x1e80100-llcc-bwmon - const: qcom,sc7280-llcc-bwmon - const: qcom,sc7280-llcc-bwmon # BWMON v5 - const: qcom,sdm845-llcc-bwmon # BWMON v5 @@ -72,7 +74,6 @@ required: - interconnects - interrupts - operating-points-v2 - - opp-table - reg additionalProperties: false @@ -100,6 +101,17 @@ allOf: reg-names: maxItems: 1 + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-cpu-bwmon + then: + required: + - opp-table + examples: - | #include <dt-bindings/interconnect/qcom,sdm845.h>
Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4 instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR path. Also make the opp-table optional for the X1E cpu-bwmon instances, since they use the same opp-table between them. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- v2: * Allow for opp-tables to be optional on X1E cpu-bwmon instances. [Konrad] * Drop Rb from Krzysztof due to more bindings changes. .../bindings/interconnect/qcom,msm8998-bwmon.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)