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Tue, 2 Jul 2024 08:15:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099DA.mail.protection.outlook.com (10.167.17.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7741.18 via Frontend Transport; Tue, 2 Jul 2024 08:15:57 +0000 Received: from shatadru.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 2 Jul 2024 03:15:53 -0500 From: Dhananjay Ugwekar To: , , , , , , , CC: , , "Dhananjay Ugwekar" , David Arcari Subject: [PATCH v2 2/2] cpufreq/amd-pstate: Fix the scaling_max_freq setting on shared memory CPPC systems Date: Tue, 2 Jul 2024 08:14:14 +0000 Message-ID: <20240702081413.5688-3-Dhananjay.Ugwekar@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240702081413.5688-1-Dhananjay.Ugwekar@amd.com> References: <20240702081413.5688-1-Dhananjay.Ugwekar@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DA:EE_|SN7PR12MB6959:EE_ X-MS-Office365-Filtering-Correlation-Id: 55fdfff2-8eff-4271-d401-08dc9a6f339c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: /ywqJ0GGjaUNDfZj3aSAZ563SkVM+QsJXgmi/lZfL72MBGTYKMITvlxyzAkw9A92uWyNFPHuribp7a6apdS+rLNrU1TyDX5685QJ2DKrq2gtXzyRGgVVK54uFK9yVsYwcJ+EvtQ2NNsiBq2zYVsFnZ5qiAeUGEtEz1eAqD69C4AJP2WX5gmTPC0p5XHIaYcQ7YbWSU9sD8uR1gfBHIsopw4IPW4Cuw4/06HZX+ARi7H1pHv1Y8FPQdT+6bqH40QtAor2MoaaFq5r3gIuTqK9BpKDSJYhQAXvuCszT8XZldTFXfkuOYINEysWnJBj+oxNGfoMM9DgIOB5jka8GpgEbZC5ES9bigrdp70JEgG8Kj+fwfyBjsKrx21L398fhOCEpqM/DJDSU/5mfUNXO9hf27L9+Fz8U+Vkot4xhnQkcpIesOsB1b/1heCXRvGEnlDPYJJ0d1cmMCdi1LGwurbTG1SOzPkkIXNiTpzm83QfP6UMPJ8BYynlc2zzuMHRaWxM09+SwezNyhVZAwvx3LBpS8Z9D6UFzJRO2BNlAKsxFYtGxeq7kGymNMs+qxbMtMsp8EXdveeiEUdvvEHHhx2AGKe8LThARibDNkN5j+CUrVHFZNeeJOVJkohKYdcLKJiAzP6SOc0VtF1bSE0ARz/TGjaymEzUzV6F8DsTI0punr37cTnKj58uQhMxZtdFmu9bgwQuhw0pEm6kovoBdp7njtv6CaaqjYkttISLdU9K1U3kxEHm21xmJpAH1G1imm184/RaArKcJeZJetKBgreoQ1C7UryLlxWj6zEV9r8tkZVHLvcuKb3YmTDET9XM9Phtjv/un5/Ke49ti0jZt0SGDwHJHlAyE8kkpPahanoVudGgxlm05w53qJVCU2DMLi7B3ZXUJ9IYsVayeCP+NyhDsie0tlpE9wx5IXyiHF/OA0480bUkbzYXqBhIvLU3tkw33Pjo0cRaSWMTEW1ESrsmcBy+MdLtm2MLkOtayrdlyUSMHohRe6aMqjdLajTnNwdaQmWeTOsiDDVZbEF00wkp2Yj3UvUtGkBjAxnwtIubO6ETnva/6R6QpQxnlXVp0Y7H6agnVJKMwK7KbqdX7fT5RqCeXuauUR3Pzpy1H/6IvKKEEUXzcbrymtI809FIJSUmcNXK/UKbBPPr9gKNPP+XtCWg0oR7lwqxwmRSA8RKr+iOxgoixPg/sdDE/BpiPPvg+G2jOBnd5PUvvx/kcJ8XPzA/kvI6GrtYfR5kqo4HlFOvHaJ6yisGnZeYeHYR9gchk6kIVnXUvtJk6SUrZ041n5zWcEn23w1gyfrVC81R0j5unq2Q4vqAii7K1BSLVCQRRSSPrHZt/ruPxrwbvAfCMyk7iGS7qwGlx/YKKmafBA/VQg2apy9OmxEVgTOvpiXCp1HVDu4pNlD3ce6R+FCVQu09bptxMxNHowod19WNiBNQrd3fMxviZWmA5GuvoO5z X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2024 08:15:57.6637 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55fdfff2-8eff-4271-d401-08dc9a6f339c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6959 On shared memory CPPC systems, with amd_pstate=active mode, the change in scaling_max_freq doesn't get written to the shared memory region. Due to this, the writes to the scaling_max_freq sysfs file don't take effect. Fix this by propagating the scaling_max_freq changes to the shared memory region. Fixes: ffa5096a7c33 ("cpufreq: amd-pstate: implement Pstate EPP support for the AMD processors") Reported-by: David Arcari Signed-off-by: Dhananjay Ugwekar Reviewed-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 43 +++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9ad62dbe8bfb..a092b13ffbc2 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -247,6 +247,26 @@ static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata) return index; } +static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, + u32 des_perf, u32 max_perf, bool fast_switch) +{ + if (fast_switch) + wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); + else + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + READ_ONCE(cpudata->cppc_req_cached)); +} + +DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf); + +static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, + u32 min_perf, u32 des_perf, + u32 max_perf, bool fast_switch) +{ + static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, + max_perf, fast_switch); +} + static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) { int ret; @@ -263,6 +283,9 @@ static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) if (!ret) cpudata->epp_cached = epp; } else { + amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, + cpudata->max_limit_perf, false); + perf_ctrls.energy_perf = epp; ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); if (ret) { @@ -452,16 +475,6 @@ static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) return static_call(amd_pstate_init_perf)(cpudata); } -static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, - u32 des_perf, u32 max_perf, bool fast_switch) -{ - if (fast_switch) - wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); - else - wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, - READ_ONCE(cpudata->cppc_req_cached)); -} - static void cppc_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) @@ -475,16 +488,6 @@ static void cppc_update_perf(struct amd_cpudata *cpudata, cppc_set_perf(cpudata->cpu, &perf_ctrls); } -DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf); - -static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, - u32 min_perf, u32 des_perf, - u32 max_perf, bool fast_switch) -{ - static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, - max_perf, fast_switch); -} - static inline bool amd_pstate_sample(struct amd_cpudata *cpudata) { u64 aperf, mperf, tsc;