From patchwork Wed Jul 3 09:16:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13721571 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB0E813E02D; Wed, 3 Jul 2024 09:18:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719998329; cv=none; b=oTUQNxwu/YjAwbZnjngm7E8JfpeG3WttuLRahWoHeSgC0IBWMZcxLvilHcWFIL8k9EuwPVZWbrD/ZoB9y3mxsVeopImNRGrb2U6SXrQ2CTd8V1EH8Trefiza9H56anViwpZGFa7PPRqx+YaO2bXo5Ll/TzrHaTPTMb4oTsm/hws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719998329; c=relaxed/simple; bh=NbghBCuv6Z9GqbuZNLOUww8AHwyziSDpjlICfOPy36A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=snJ+d2j9j3rNiA8pwebJE56yePIj9+ytfMumbGqxf6LWLZLkfYl0ygwh7rqvNIPQIsxzFhkuXBkMH/9JELzDrRIA6JEyPaNsrtcLCGyO1hoUCYwEL8az+30n9Sv+BismOSHsCqAQDfJtUAcnyl7Dljnzxn704auTYjBap7NLgxY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=f37jQhkj; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="f37jQhkj" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4632V6qH028807; Wed, 3 Jul 2024 09:18:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= b7L/FBiJ5rwG+vtCCzRfyxibTJlnj405qJWswdSeEWc=; b=f37jQhkj/pT7afk4 HIIb9Wzkabkxs/F+btN4sMLJBxrlMIBR2scTIY/UarIeA8JAj/Pmc49WngyOZazg jEWvM7p5s2P7Su/Wix8fweQNYA/LDlL9izQFc4QstG7pS9bYyFiyKRdmhOaQ3Tn3 AQSJe8vXZqY7MK1PCzgcjFJVzkTigbsVjC89bX0ff8MJYvAw6cxfzOkuFZK2p98f 39y1H20+Sgdt2gY0Ujqtl3rRsX5J+JJd93B+aynW5CJ0wE+Siv8PwFlzXuaV5SZ+ HnPfxJEn1DMQPlDgm64THcY+ByxlT3ffUpne8wmZXJuilKfpUGPrCuSjJ7ywcBRg 6FHJhg== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 404kctjkqs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 03 Jul 2024 09:18:24 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4639IN2t026730 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Jul 2024 09:18:23 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 3 Jul 2024 02:18:15 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Dmitry Baryshkov Subject: [PATCH v4 07/10] clk: qcom: gcc-ipq9574: Add CPR clock definition Date: Wed, 3 Jul 2024 14:46:48 +0530 Message-ID: <20240703091651.2820236-8-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240703091651.2820236-1-quic_varada@quicinc.com> References: <20240703091651.2820236-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _HfGQi6uugmlhsyPQRKiBIkoFymf7vBi X-Proofpoint-ORIG-GUID: _HfGQi6uugmlhsyPQRKiBIkoFymf7vBi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-03_05,2024-07-02_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407030068 Add the CPR clock definition needed for enabling access to CPR register space. Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan --- drivers/clk/qcom/gcc-ipq9574.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index e1dc74d04ed1..eac557937fd3 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = { }, }; +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_xo_map, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_map), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rbcpr_clk", + .parent_hws = (const struct clk_hw *[]) { + &rbcpr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_hw *gcc_ipq9574_hws[] = { &gpll0_out_main_div2.hw, &gcc_xo_div4_clk_src.hw, @@ -4219,6 +4256,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GCC_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, + [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = {