From patchwork Tue Oct 8 13:20:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13826479 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 021991E04AE; Tue, 8 Oct 2024 13:23:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728393819; cv=none; b=dboQIzCkqhpt2Vsf/411vGPvxYI3WALr4/Ima3K/qdAEuQTN2Yit+rwgNNx5Ct/fN6ZhanFKCAsB74Z8BX+a5pZ3UIPA7HNoVcGFslKDMiPa3qqOFHr5H6XQXxeZ7MAl/tve4l9Ays05/o9yV/HkSgRf+5FmDLcrFf/p0sSxrh8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728393819; c=relaxed/simple; bh=bjb7r4yD7kLildjXyl2GEvt+BBnyJaCMMAQzlo/RA6s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LGAablcQDumD7Jadc77HFEJ4L6hzTriiqkxrpdVfIV1QkW4CB0LlaJTXloAqUg/oAyCv8s+CAYZ/wSHcbzdTqWMo55uaHQlE4cPp1PX12yk8TMCpL1Izgz1ULKHVqJIgc4E8zKuMv26ofLWXjhobWKFt0mLSRes5pNqHr+WQFKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=J9Uqur8g; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="J9Uqur8g" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 498DNRBx056172; Tue, 8 Oct 2024 08:23:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1728393807; bh=HrD4Ku9zamDWSQfcwl8FJdXLdDdZm3d+Gbi86KRDaN4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=J9Uqur8gqN8NVNpfYd0bDJEPvbHU1YifsUshqvuAjh6ID+3sIllxKze3M28S0rFbo XwDO69Mt8tJZkLBk0pQunnSpoVJo87XCt/5sNEvXUV2/1V6obROTTLJ1q8uTHSRZoC AcLgQu+f2eGBwHWpRaBWbJat1XJndRK+GyairrgM= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 498DNQJb097979 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2024 08:23:26 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Oct 2024 08:23:26 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Oct 2024 08:23:26 -0500 Received: from lcpd911.dhcp.ti.com (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 498DN82E098273; Tue, 8 Oct 2024 08:23:23 -0500 From: Dhruva Gole To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo CC: , , , , Dhruva Gole , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof Subject: [PATCH V8 2/4] arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry Date: Tue, 8 Oct 2024 18:50:51 +0530 Message-ID: <20241008132052.407994-3-d-gole@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008132052.407994-1-d-gole@ti.com> References: <20241008132052.407994-1-d-gole@ti.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Bryan Brattlof The AM62Ax reference board is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 7.5 of the SoC's data sheet[0]. Append the 1.4Ghz entry to the OPP table to enable this OPP [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Bryan Brattlof Signed-off-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 67faf46d7a35..a6f0d87a50d8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -68,6 +68,15 @@ wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + vmain_pd: regulator-0 { /* TPS25750 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed";