diff mbox series

intel_idle: add Granite Rapids Xeon D support

Message ID 20241107115608.52233-1-artem.bityutskiy@linux.intel.com (mailing list archive)
State In Next
Delegated to: Rafael Wysocki
Headers show
Series intel_idle: add Granite Rapids Xeon D support | expand

Commit Message

Artem Bityutskiy Nov. 7, 2024, 11:56 a.m. UTC 
Add Granite Rapids Xeon C C-states support: C1, C1E, C6, and C6P.

The C-states are basically the same as in Granite Rapids Xeon SP/AP, but
characteristics (latency, target residency) are a bit different.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
---
 drivers/idle/intel_idle.c | 48 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)


base-commit: ff7afaeca1a15fbeaa2c4795ee806c0667bd77b2

Comments

Artem Bityutskiy Nov. 7, 2024, 11:59 a.m. UTC | #1 
On Thu, 2024-11-07 at 13:56 +0200, Artem Bityutskiy wrote:
> Add Granite Rapids Xeon C C-states support: C1, C1E, C6, and C6P.

Oh, just noticed a typo - should be Granite Rapids Xeon D, sorry. Rafael, if you
pick this patch, please amend the commit message. Alternatively, I can send an
adjusted version. Thanks!

Artem.
Rafael J. Wysocki Nov. 11, 2024, 2:51 p.m. UTC | #2 
On Thu, Nov 7, 2024 at 12:59 PM Artem Bityutskiy <dedekind1@gmail.com> wrote:
>
> On Thu, 2024-11-07 at 13:56 +0200, Artem Bityutskiy wrote:
> > Add Granite Rapids Xeon C C-states support: C1, C1E, C6, and C6P.

Applied as 6.13 material.

> Oh, just noticed a typo - should be Granite Rapids Xeon D, sorry. Rafael, if you
> pick this patch, please amend the commit message.

Done, thanks!

> Alternatively, I can send an adjusted version. Thanks!
diff mbox series

Patch

diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 67aebfe0fed6..ac4d8faa3886 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -1069,6 +1069,47 @@  static struct cpuidle_state gnr_cstates[] __initdata = {
 		.enter = NULL }
 };
 
+static struct cpuidle_state gnrd_cstates[] __initdata = {
+	{
+		.name = "C1",
+		.desc = "MWAIT 0x00",
+		.flags = MWAIT2flg(0x00),
+		.exit_latency = 1,
+		.target_residency = 1,
+		.enter = &intel_idle,
+		.enter_s2idle = intel_idle_s2idle, },
+	{
+		.name = "C1E",
+		.desc = "MWAIT 0x01",
+		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
+		.exit_latency = 4,
+		.target_residency = 4,
+		.enter = &intel_idle,
+		.enter_s2idle = intel_idle_s2idle, },
+	{
+		.name = "C6",
+		.desc = "MWAIT 0x20",
+		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED |
+					   CPUIDLE_FLAG_INIT_XSTATE |
+					   CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
+		.exit_latency = 220,
+		.target_residency = 650,
+		.enter = &intel_idle,
+		.enter_s2idle = intel_idle_s2idle, },
+	{
+		.name = "C6P",
+		.desc = "MWAIT 0x21",
+		.flags = MWAIT2flg(0x21) | CPUIDLE_FLAG_TLB_FLUSHED |
+					   CPUIDLE_FLAG_INIT_XSTATE |
+					   CPUIDLE_FLAG_PARTIAL_HINT_MATCH,
+		.exit_latency = 240,
+		.target_residency = 750,
+		.enter = &intel_idle,
+		.enter_s2idle = intel_idle_s2idle, },
+	{
+		.enter = NULL }
+};
+
 static struct cpuidle_state atom_cstates[] __initdata = {
 	{
 		.name = "C1E",
@@ -1508,6 +1549,12 @@  static const struct idle_cpu idle_cpu_gnr __initconst = {
 	.use_acpi = true,
 };
 
+static const struct idle_cpu idle_cpu_gnrd __initconst = {
+	.state_table = gnrd_cstates,
+	.disable_promotion_to_c1e = true,
+	.use_acpi = true,
+};
+
 static const struct idle_cpu idle_cpu_avn __initconst = {
 	.state_table = avn_cstates,
 	.disable_promotion_to_c1e = true,
@@ -1593,6 +1640,7 @@  static const struct x86_cpu_id intel_idle_ids[] __initconst = {
 	X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X,	&idle_cpu_spr),
 	X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X,	&idle_cpu_spr),
 	X86_MATCH_VFM(INTEL_GRANITERAPIDS_X,	&idle_cpu_gnr),
+	X86_MATCH_VFM(INTEL_GRANITERAPIDS_D,	&idle_cpu_gnrd),
 	X86_MATCH_VFM(INTEL_XEON_PHI_KNL,	&idle_cpu_knl),
 	X86_MATCH_VFM(INTEL_XEON_PHI_KNM,	&idle_cpu_knl),
 	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT,	&idle_cpu_bxt),