@@ -134,6 +134,17 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
if (bw == gmu->gpu_bw_table[bw_index])
break;
}
+
+ if (bw_index) {
+ /*
+ * Append AB vote to the maximum bus usage.
+ * AB represents a quantitized 16bit value of the
+ * max ddr bandwidth we could use, let's simply
+ * request the maximum for now.
+ */
+ bw_index |= AB_VOTE(MAX_AB_VOTE);
+ bw_index |= AB_VOTE_ENABLE;
+ }
}
gmu->current_perf_index = perf_index;
@@ -173,6 +173,11 @@ struct a6xx_hfi_gx_bw_perf_vote_cmd {
u32 bw;
};
+#define AB_VOTE_MASK GENMASK(31, 16)
+#define MAX_AB_VOTE (FIELD_MAX(AB_VOTE_MASK) - 1)
+#define AB_VOTE(vote) FIELD_PREP(AB_VOTE_MASK, (vote))
+#define AB_VOTE_ENABLE BIT(8)
+
#define HFI_H2F_MSG_PREPARE_SLUMBER 33
struct a6xx_hfi_prep_slumber_cmd {
When requesting a DDR bandwidth level along a GPU frequency level via the GMU, we can also specify the bus bandwidth usage in a 16bit quantitized value. For now simply request the maximum bus usage. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 +++++++++++ drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 5 +++++ 2 files changed, 16 insertions(+)