From patchwork Mon Nov 25 21:20:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 13885301 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A12018E750; Mon, 25 Nov 2024 21:21:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732569669; cv=none; b=qF5Tu1PVSGRbbyDW4Ptk0CltPlVLGmf4kGVpbr4bCCti7DSgaUAc3wMQtYRtcZQrmaXI2PBMB9NoMDZMpAc6C3qJYK4f9IVhztW46sphxFmX2ywPepckbT246R/fHibPTxinblLKyEC3lIFtQ0BBnAEEb7FgMCTITchowqAC3fs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732569669; c=relaxed/simple; bh=EbU1FkO6EYijb343nJFoDhZqvEu0zf0KCIAbfgn42Xw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DpivnAFOGcK8QYa1A5Mx7I1PgZnyOQElo2OizVixBMRtcyljdjfsgxZcBToVee60HB/RX+WgE0nfZZ/HyDggdX4EWv0YSV60kq9GL8d11zA0hpDxsweYV6HSrB8UrQDkkO0I0jezN0wq17JknJwEq/TbA7AZKP+mx4Q2E5jcEw0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=cYSZKifU; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="cYSZKifU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1732569664; bh=EbU1FkO6EYijb343nJFoDhZqvEu0zf0KCIAbfgn42Xw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cYSZKifUQQN5mrNK0fzJFFSEj8eJI9g73B6yRi8Si6HZNxMeDsXOiJfaBTv6FUtt2 nEc5BtB9M8ME9OKync3MIhlpW6m/lyJ54JR9E8IwDfgIrhSEXdY8kQ1MhaAc8mLOmK nqXG4qPefmtjLdhj16jcWfsZnjInlHRwbGbbX3Q4DA3lFLIPo/k8WtmFXdNLGXhafi 2ae8c6IV4D9e5UavYpnDpPRJfNRgAhOuqIfcZTWY9XYFVuObVVVKXKZGoSvO/K9P9a k9ohPU7wCPuOA5KB3AimtoBCgAW6FRH1E+chQ6G+gpWjZzyIgk+6l1YcFo88YrDwJp Lx4bLaRtZ5oKw== Received: from [192.168.1.63] (pool-100-2-116-133.nycmny.fios.verizon.net [100.2.116.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4C1A517E37D0; Mon, 25 Nov 2024 22:21:02 +0100 (CET) From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= Date: Mon, 25 Nov 2024 16:20:30 -0500 Subject: [PATCH 3/5] thermal/drivers/mediatek/lvts: Disable low offset IRQ for minimum threshold Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241125-mt8192-lvts-filtered-suspend-fix-v1-3-42e3c0528c6c@collabora.com> References: <20241125-mt8192-lvts-filtered-suspend-fix-v1-0-42e3c0528c6c@collabora.com> In-Reply-To: <20241125-mt8192-lvts-filtered-suspend-fix-v1-0-42e3c0528c6c@collabora.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Matthias Brugger , AngeloGioacchino Del Regno , Alexandre Mergnat , Balsam CHIHI Cc: kernel@collabora.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Hsin-Te Yuan , Chen-Yu Tsai , =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= , "Rafael J. Wysocki" , =?utf-8?b?TsOtY29sYXMg?= =?utf-8?b?Ri4gUi4gQS4gUHJhZG8=?= , stable@vger.kernel.org X-Mailer: b4 0.14.2 In order to get working interrupts, a low offset value needs to be configured. The minimum value for it is 20 Celsius, which is what is configured when there's no lower thermal trip (ie the thermal core passes -INT_MAX as low trip temperature). However, when the temperature gets that low and fluctuates around that value it causes an interrupt storm. Prevent that interrupt storm by not enabling the low offset interrupt if the low threshold is the minimum one. Cc: stable@vger.kernel.org Fixes: 77354eaef821 ("thermal/drivers/mediatek/lvts_thermal: Don't leave threshold zeroed") Signed-off-by: Nícolas F. R. A. Prado --- drivers/thermal/mediatek/lvts_thermal.c | 48 ++++++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 6ac33030f015c7239e36d81018d1a6893cb69ef8..2271023f090df82fbdd0b5755bb34879e58b0533 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -67,10 +67,14 @@ #define LVTS_CALSCALE_CONF 0x300 #define LVTS_MONINT_CONF 0x0300318C -#define LVTS_MONINT_OFFSET_SENSOR0 0xC -#define LVTS_MONINT_OFFSET_SENSOR1 0x180 -#define LVTS_MONINT_OFFSET_SENSOR2 0x3000 -#define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 +#define LVTS_MONINT_OFFSET_HIGH_SENSOR0 BIT(3) +#define LVTS_MONINT_OFFSET_HIGH_SENSOR1 BIT(8) +#define LVTS_MONINT_OFFSET_HIGH_SENSOR2 BIT(13) +#define LVTS_MONINT_OFFSET_HIGH_SENSOR3 BIT(25) +#define LVTS_MONINT_OFFSET_LOW_SENSOR0 BIT(2) +#define LVTS_MONINT_OFFSET_LOW_SENSOR1 BIT(7) +#define LVTS_MONINT_OFFSET_LOW_SENSOR2 BIT(12) +#define LVTS_MONINT_OFFSET_LOW_SENSOR3 BIT(24) #define LVTS_INT_SENSOR0 0x0009001F #define LVTS_INT_SENSOR1 0x001203E0 @@ -326,11 +330,17 @@ static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) { - u32 masks[] = { - LVTS_MONINT_OFFSET_SENSOR0, - LVTS_MONINT_OFFSET_SENSOR1, - LVTS_MONINT_OFFSET_SENSOR2, - LVTS_MONINT_OFFSET_SENSOR3, + u32 high_offset_masks[] = { + LVTS_MONINT_OFFSET_HIGH_SENSOR0, + LVTS_MONINT_OFFSET_HIGH_SENSOR1, + LVTS_MONINT_OFFSET_HIGH_SENSOR2, + LVTS_MONINT_OFFSET_HIGH_SENSOR3, + }; + u32 low_offset_masks[] = { + LVTS_MONINT_OFFSET_LOW_SENSOR0, + LVTS_MONINT_OFFSET_LOW_SENSOR1, + LVTS_MONINT_OFFSET_LOW_SENSOR2, + LVTS_MONINT_OFFSET_LOW_SENSOR3, }; u32 value = 0; int i; @@ -339,10 +349,22 @@ static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) for (i = 0; i < ARRAY_SIZE(masks); i++) { if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh - && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) - value |= masks[i]; - else - value &= ~masks[i]; + && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) { + /* + * The minimum threshold needs to be configured in the + * OFFSETL register to get working interrupts, but we + * don't actually want to generate interrupts when + * crossing it. + */ + if (lvts_ctrl->low_thresh == -INT_MAX) { + value &= ~low_offset_masks[i]; + value |= high_offset_masks[i]; + } else { + value |= low_offset_masks[i] | high_offset_masks[i]; + } + } else { + value &= ~(low_offset_masks[i] | high_offset_masks[i]); + } } writel(value, LVTS_MONINT(lvts_ctrl->base));