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[93.34.91.161]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-434b0dc6831sm154173915e9.20.2024.12.02.07.13.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 07:13:03 -0800 (PST) From: Christian Marangi To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@airoha.com Subject: [PATCH v4 1/2] dt-bindings: cpufreq: Document support for Airoha EN7581 CPUFreq Date: Mon, 2 Dec 2024 16:12:03 +0100 Message-ID: <20241202151228.32609-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document required property for Airoha EN7581 CPUFreq . On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS. The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables. Signed-off-by: Christian Marangi Reviewed-by: Ulf Hansson --- Changes v4: - Add this patch .../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml b/Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file mode 100644 index 000000000000..a5bdea7f34b5 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml @@ -0,0 +1,259 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/airoha,en7581-cpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 CPUFreq + +maintainers: + - Christian Marangi + +description: | + On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands + to ATF and no clocks are exposed to the OS. + + The SoC have performance state described by ID for each OPP, for this a + Power Domain is used that sets the performance state ID according to the + required OPPs defined in the CPU OPP tables. + +properties: + compatible: + const: airoha,en7581-cpufreq + + '#clock-cells': + const: 0 + + '#power-domain-cells': + const: 0 + + operating-points-v2: true + +required: + - compatible + - '#clock-cells' + - '#power-domain-cells' + - operating-points-v2 + +additionalProperties: false + +examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&smcc_opp0>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + required-opps = <&smcc_opp1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&smcc_opp2>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&smcc_opp3>; + }; + + opp-7000000000 { + opp-hz = /bits/ 64 <700000000>; + required-opps = <&smcc_opp4>; + }; + + opp-7500000000 { + opp-hz = /bits/ 64 <750000000>; + required-opps = <&smcc_opp5>; + }; + + opp-8000000000 { + opp-hz = /bits/ 64 <800000000>; + required-opps = <&smcc_opp6>; + }; + + opp-8500000000 { + opp-hz = /bits/ 64 <850000000>; + required-opps = <&smcc_opp7>; + }; + + opp-9000000000 { + opp-hz = /bits/ 64 <900000000>; + required-opps = <&smcc_opp8>; + }; + + opp-9500000000 { + opp-hz = /bits/ 64 <950000000>; + required-opps = <&smcc_opp9>; + }; + + opp-10000000000 { + opp-hz = /bits/ 64 <1000000000>; + required-opps = <&smcc_opp10>; + }; + + opp-10500000000 { + opp-hz = /bits/ 64 <1050000000>; + required-opps = <&smcc_opp11>; + }; + + opp-11000000000 { + opp-hz = /bits/ 64 <1100000000>; + required-opps = <&smcc_opp12>; + }; + + opp-11500000000 { + opp-hz = /bits/ 64 <1150000000>; + required-opps = <&smcc_opp13>; + }; + + opp-12000000000 { + opp-hz = /bits/ 64 <1200000000>; + required-opps = <&smcc_opp14>; + }; + }; + + cpu_smcc_opp_table: opp-table-cpu-smcc { + compatible = "operating-points-v2"; + + smcc_opp0: opp0 { + opp-level = <0>; + }; + + smcc_opp1: opp1 { + opp-level = <1>; + }; + + smcc_opp2: opp2 { + opp-level = <2>; + }; + + smcc_opp3: opp3 { + opp-level = <3>; + }; + + smcc_opp4: opp4 { + opp-level = <4>; + }; + + smcc_opp5: opp5 { + opp-level = <5>; + }; + + smcc_opp6: opp6 { + opp-level = <6>; + }; + + smcc_opp7: opp7 { + opp-level = <7>; + }; + + smcc_opp8: opp8 { + opp-level = <8>; + }; + + smcc_opp9: opp9 { + opp-level = <9>; + }; + + smcc_opp10: opp10 { + opp-level = <10>; + }; + + smcc_opp11: opp11 { + opp-level = <11>; + }; + + smcc_opp12: opp12 { + opp-level = <12>; + }; + + smcc_opp13: opp13 { + opp-level = <13>; + }; + + smcc_opp14: opp14 { + opp-level = <14>; + }; + }; + + cpufreq: cpufreq { + compatible = "airoha,en7581-cpufreq"; + + operating-points-v2 = <&cpu_smcc_opp_table>; + + #power-domain-cells = <0>; + #clock-cells = <0>; + }; + };