From patchwork Fri May 12 02:00:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Len Brown X-Patchwork-Id: 9723431 X-Patchwork-Delegate: rjw@sisk.pl Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 78380600CB for ; Fri, 12 May 2017 02:01:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 70A6028801 for ; Fri, 12 May 2017 02:01:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6539928803; Fri, 12 May 2017 02:01:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E8E0628801 for ; Fri, 12 May 2017 02:01:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757614AbdELCBB (ORCPT ); Thu, 11 May 2017 22:01:01 -0400 Received: from mail-qt0-f194.google.com ([209.85.216.194]:33819 "EHLO mail-qt0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757585AbdELCA7 (ORCPT ); Thu, 11 May 2017 22:00:59 -0400 Received: by mail-qt0-f194.google.com with SMTP id l39so5184745qtb.1; Thu, 11 May 2017 19:00:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:reply-to:organization; bh=OJnpbn1aFmF97rIux1fX6WoYZfL5Xp/5BXYXSRxk2zg=; b=lq601M3yJ1Bk3BXkaIjV6brM2Gdt01584fCB5SnVAVPzO/oTSryiDWzLOt7m70wlT3 KwhKdWTKTAgvHhqg8TQsNbIzRhWKAB7NXPT0DfRs9x7lsrIAwvcsEOqXCdo5R7YmCD2W 0utaDw6joKchTbRK0pIJLaNkWyISoEeShhuev/ub/CW4Cv8XjO8MdBjoGmZZO4x8CC+e W2OXGXUH0J/MipoWJq+XUJwTFchI0SqL8bx/yoYIC8q7W38i56d03CyEUUmyaacaBv51 P4SVwBs075sW9CvRuZS285N9AXNDA1WqYxIFZLGdr7/LHK8Wz34Lt6uOmZNizOUWUQwC QFjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references:reply-to:organization; bh=OJnpbn1aFmF97rIux1fX6WoYZfL5Xp/5BXYXSRxk2zg=; b=sPN3QrZWhXdDCgD+E20f9KgMpxaxj5SEEbdvyhra6MOlN4z/4bJCRZSJ+dS+hANHAP K36yGtIJOmL+M35KKzE+wSyzAydGUa6KpoywNozd3ozQyJ7PARh7LCP0y6AzZcPxxrRD RpIYFzLi+lHvKzyNzy+/SFQ5YswVqdgR9ZPXIXyB0Wm17YySvjJq0/nnOpf1dYimBzvO WZkA0D+p0e5OsBhfl/Fzo6/GQ7JiKYjTUY8pexQyJWpR4VbxKkHvYmWCRfJRKUNyfJrY BKRV6Kkh4/cW7GmyG/y0wXUn1DmUBtdIIBOMhmncSIqZdnmhwPEfC66d3OD98KFbFv9s 2pwA== X-Gm-Message-State: AODbwcD0WMsTpH0yvbMbfaRDoILpn4DQq7GWrm0SrPfXS+iSSKRNlThV kaw6To5dZyb8Lg== X-Received: by 10.200.52.83 with SMTP id v19mr1478265qtb.214.1494554458254; Thu, 11 May 2017 19:00:58 -0700 (PDT) Received: from z87.localdomain (h96-61-81-193.cntcnh.dsl.dynamic.tds.net. [96.61.81.193]) by smtp.gmail.com with ESMTPSA id s7sm1375104qtb.35.2017.05.11.19.00.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 11 May 2017 19:00:57 -0700 (PDT) From: Len Brown To: rjw@rjwysocki.net, linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Len Brown Subject: [PATCH 2/5] x86: msr-index.h: define HWP.EPP values Date: Thu, 11 May 2017 22:00:20 -0400 Message-Id: <8d84e906f5db80540510e448226f2718a686eb2a.1494552477.git.len.brown@intel.com> X-Mailer: git-send-email 2.11.0.161.g6610af872 In-Reply-To: <20170512020023.23204-1-lenb@kernel.org> References: <20170512020023.23204-1-lenb@kernel.org> In-Reply-To: References: Reply-To: Len Brown Organization: Intel Open Source Technology Center Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Len Brown The Hardware Performance State request MSR has a field to express the "Energy Performance Preference" (HWP.EPP). Decode that field so the definition may be shared by by the intel_pstate driver and any utilities that decode the same register. Signed-off-by: Len Brown --- arch/x86/include/asm/msr-index.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a92d9bd154f6..50c0c3204a92 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -239,6 +239,10 @@ #define HWP_MAX_PERF(x) ((x & 0xff) << 8) #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) +#define HWP_EPP_PERFORMANCE 0x00 +#define HWP_EPP_BALANCE_PERFORMANCE 0x80 +#define HWP_EPP_BALANCE_POWERSAVE 0xC0 +#define HWP_EPP_POWERSAVE 0xFF #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42)